55 lines
2.0 KiB
ReStructuredText
55 lines
2.0 KiB
ReStructuredText
Bus Decoder Architecture
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========================
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The generated RTL is a pure bus-routing layer. It accepts a single CPU interface
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on the slave side and fans transactions out to a set of child interfaces on the
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master side. No register storage or field logic is generated.
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Although you do not need to know the inner workings to use the exporter, the
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sections below explain the structure of the generated module and how it maps to
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SystemRDL hierarchy.
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CPU Interface Adapter
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---------------------
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Each supported CPU interface protocol (APB3, APB4, AXI4-Lite) provides a small
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adapter that translates the external bus protocol into internal request/response
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signals. These internal signals are then used by the address decoder and fanout
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logic.
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If you write a custom CPU interface, it must implement the internal signals
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described in :ref:`cpuif_protocol`.
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Address Decode
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--------------
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The address decoder computes per-child select signals based on address ranges.
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The decode boundary is controlled by ``max_decode_depth``:
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* ``0``: Decode all the way down to leaf registers
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* ``1`` (default): Decode only top-level children
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* ``N``: Decode down to depth ``N`` from the top-level
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This allows you to choose whether the bus decoder routes to large blocks (e.g.,
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child addrmaps) or to smaller sub-blocks.
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Fanout to Child Interfaces
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--------------------------
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For each decoded child, the bus decoder drives a master-side CPU interface.
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All address, data, and control signals are forwarded to the selected child.
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Arrayed children can be kept as arrays or unrolled into discrete interfaces using
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``--unroll``. This only affects port structure and naming; decode semantics are
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unchanged.
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Fanin and Error Handling
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------------------------
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Read and write responses are muxed back from the selected child to the slave
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interface. If no child is selected for a transaction, the decoder generates an
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error response on the slave interface.
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The exact error signaling depends on the chosen CPU interface protocol (e.g.,
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``PSLVERR`` for APB, ``RRESP/BRESP`` for AXI4-Lite).
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