52 lines
2.1 KiB
Plaintext
52 lines
2.1 KiB
Plaintext
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Port Declaration
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Generates the port declaration of the module:
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- Parameters
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- rd/wr error response/data behavior
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Do missed accesses cause a SLVERR?
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Do reads respond with a magic value?
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- Pipeline enables
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Enable reg stages in various places
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- RDL-derived Parameters:
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Someday in the future if i ever get around to this: https://github.com/SystemRDL/systemrdl-compiler/issues/58
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- Clock/Reset
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Single clk
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One or more resets
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- CPU Bus Interface
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Given the bus interface object, emits the IO
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This can be flattened ports, or a SV Interface
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Regardless, it shall be malleable so that the user can use their favorite
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declaration style
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- Hardware interface
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Two options:
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- 2-port struct interface
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Everything is rolled into two unpacked structs - inputs and outputs
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- Flattened --> NOT DOING
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Flatten/Unroll everything
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No. not doing. I hate this and dont want to waste time implementing this.
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This will NEVER be able to support parameterized regmaps, and just
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creates a ton of corner cases i dont care to deal with.
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Other IO Signals I need to be aware of:
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any signals declared, and used in any references:
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field.resetsignal
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field.next
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... etc ...
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any signals declared and marked as cpuif_reset, or field_reset
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These override the default rst
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If both are defined, be sure to not emit the default
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Pretty straightforward (see 17.1)
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Also have some notes on this in my general Logbook
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Will have to make a call on how these propagate if multiple defined
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in different hierarchies
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interrupt/halt outputs
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See "Interrupts" logbook for explanation
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addrmap.errextbus, regfile.errextbus, reg.errextbus
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???
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Apparently these are inputs
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