104 lines
3.7 KiB
Plaintext
104 lines
3.7 KiB
Plaintext
================================================================================
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Summary
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================================================================================
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RTL interface that provides access to per-field context signals
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Regarding signals:
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RDL-declared signals are part of the hwif input structure.
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Only include them if they are referenced by the design (need to scan the
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full design anyways, so may as well filter out unreferenced ones)
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It is possible to use signals declared in a parent scope.
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This means that not all signals will be discovered by a hierarchical listener alone
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Need to scan ALL assigned properties for signal references too.
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- get signal associated with top node's cpuif_reset helper property, if any
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- collect all field_resets
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X check all signal instances in the hier tree
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- search parents of top node for the first field_reset signal, if any
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This is WAY less expensive than querying EACH field's resetsignal property
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X Check all explicitly assigned properties
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only need to do this for fields
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Collect all of these into the following:
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- If inside the hier, add to a list of paths
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- if outside the hier, add to a dict of path:SignalNode
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These are all the signals in-use by the design
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Pass list into the hwif generator
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If the hwif generator encounters a signal during traversal:
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check if it exists in the signal path list
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out-of-hier signals are inserted outside of the hwif_in as standalone signals.
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For now, just use their plain inst names. If I need to uniquify them i can add that later.
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I should at least check against a list of known "dirty words". Seems very likely someone will choose
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a signal called "rst".
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Prefix with usersig_ if needed
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================================================================================
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Naming Scheme
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================================================================================
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hwif_out
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.my_regblock
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.my_reg[X][Y]
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.my_field
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.value
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.anded
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hwif_in
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.my_regblock
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.my_reg[X][Y]
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.my_field
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.value
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.we
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.my_signal
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.my_fieldreset_signal
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================================================================================
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Flattened mode? --> NO
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================================================================================
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If user wants a flattened list of ports,
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still use the same hwif_in/out struct internally.
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Rather than declaring hwif_in and hwif_out in the port list, declare it internally
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Add a mapping layer in the body of the module that performs a ton of assign statements
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to map flat signals <-> struct
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Alternatively, don't do this at all.
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If I want to add a flattened mode, generate a wrapper module instead.
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Marking this as YAGNI for now.
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================================================================================
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IO Signals
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================================================================================
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Outputs:
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field value
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If hw readable
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bitwise reductions
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if anded, ored, xored == True, output a signal
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swmod/swacc
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event strobes
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Inputs:
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field value
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If hw writable
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we/wel
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if either is boolean, and true
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not part of external hwif if reference
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mutually exclusive
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hwclr/hwset
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if either is boolean, and true
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not part of external hwif if reference
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incr/decr
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if counter=true, generate BOTH
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incrvalue/decrvalue
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if either incrwidth/decrwidth are set
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signals!
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any signal instances instantiated in the scope
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