73 lines
2.7 KiB
Plaintext
73 lines
2.7 KiB
Plaintext
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CPU Bus interface layer
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Provides an abstraction layer between the outside SoC's bus interface, and the
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internal register block's implementation.
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Converts a user-selectable bus protocol to generic register file signals.
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Upstream Signals:
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Signal names are defined in the bus interface class and shall be malleable
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to the user.
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User can choose a flat signal interface, or a SV interface.
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SV interface shall be easy to tweak since various orgs will use different
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naming conventions in their library of interface definitions
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Downstream Signals:
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- cpuif_req
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- Single-cycle pulse
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- Qualifies the following child signals:
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- cpuif_req_is_wr
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1 denotes this is a write transfer
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- cpuif_addr
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Byte address
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- cpuif_wr_data
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- cpuif_wr_biten
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per-bit strobes
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some protocols may opt to tie this to all 1's
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- cpuif_rd_ack
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- Single-cycle pulse
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- Qualifies the following child signals:
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- cpuif_rd_data
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- cpuif_rd_err
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- cpuif_wr_ack
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- Single-cycle pulse
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- Qualifies the following child signals:
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- cpuif_wr_err
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Misc thoughts
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- Internal cpuif_* signals use a strobe-based protocol:
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- Unknown, but fixed latency
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- Makes for easy pipelining if needed
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- Decided to keep cpuif_req signals common for read write:
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This will allow address decode logic to be shared for read/write
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Downside is split protocols like axi-lite can't have totally separate rd/wr
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access lanes, but who cares?
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- separate response strobes
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Not necessary to use, but this lets me independently pipeline read/write paths.
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read path will need more time if readback mux is large
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- On multiple outstanding transactions
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Currently, cpuif doesnt really support this. Goal was to make it easily pipelineable
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without having to backfeed stall logic.
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Could still be possible to do a "fly-by" pipeline with a more intelligent cpuif layer
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Not worrying about this now.
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Implementation:
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Implement this mainly as a Jinja template.
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Upstream bus intf signals are fetched via busif class properties. Ex:
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{{busif.signal('pready')}} <= '1;
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This allows the actual SV or flattened signal to be emitted
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What protocols do I care about?
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- AXI4 Lite
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- Ignore AxPROT?
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- APB3
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- APB4
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- Ignore pprot?
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- AHB?
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- Wishbone
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- Generic
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breakout the above signals as-is (reassign with a prefix or something)
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