52 lines
2.2 KiB
Plaintext
52 lines
2.2 KiB
Plaintext
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Address Decode layer
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A bunch of combinational address decodes that generate individual register
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req strobes
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Possible decode logic styles:
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- Big case statement
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+ Probably more sim-efficient
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- Hard to do loop parameterization
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- More annoying to do multiple regs per address
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- Big always_comb + One if/else chain
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+ Easy to nest loops & parameterize if needed
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- sim has a lot to evaluate each time
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- More annoying to do multiple regs per address
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- implies precedence? Synth tools should be smart enough?
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- Big always_comb + inline conditionals <---- DO THIS
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+ Easy to nest loops & parameterize if needed
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- sim has a lot to evaluate each time
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+ Multiple regs per address possible
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+ implies address decode parallelism.
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?? Should I try using generate loops + assigns?
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This would be more explicit parallelism, however some tools may
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get upset at multiple assignments to a common struct
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Implementation:
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Jinja is inappropriate here
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Very logic-heavy. Jinja may end up being annoying
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Also, not much need for customization here
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This may even make sense as a visitor that dumps lines
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- visit each reg
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- upon entering an array, create for loops
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- upon exiting an array, emit 'end'
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Make the strobe struct declared locally
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No need for it to leave the block
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Error handling
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If no strobe generated, respond w error?
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This is actually pretty expensive to do for writes.
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Hold off on this for now.
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Reads get this effectively for free in the readback mux.
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Implement write response strobes back upstream to cpuif
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Eventually allow for optional register stage for strobe struct
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Will need to also pipeline the other cpuif signals
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ok to discard the cpuif_addr. no longer needed
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Downstream Signals:
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- access strobes
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Encase these into a struct datatype
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- is_write + wr_data/wr_bitstrobe
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