60 lines
3.0 KiB
Systemverilog
60 lines
3.0 KiB
Systemverilog
{%- if cpuif.is_interface -%}
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`ifndef SYNTHESIS
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initial begin
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// Width checks (AXI4-Lite)
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assert_bad_awaddr_width: assert($bits({{cpuif.signal("AWADDR")}}) >= {{ds.package_name}}::{{ds.module_name|upper}}_MIN_ADDR_WIDTH)
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else $error("AWADDR width %0d < MIN_ADDR_WIDTH %0d",
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$bits({{cpuif.signal("AWADDR")}}), {{ds.package_name}}::{{ds.module_name|upper}}_MIN_ADDR_WIDTH);
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assert_bad_araddr_width: assert($bits({{cpuif.signal("ARADDR")}}) >= {{ds.package_name}}::{{ds.module_name|upper}}_MIN_ADDR_WIDTH)
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else $error("ARADDR width %0d < MIN_ADDR_WIDTH %0d",
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$bits({{cpuif.signal("ARADDR")}}), {{ds.package_name}}::{{ds.module_name|upper}}_MIN_ADDR_WIDTH);
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assert_bad_data_width: assert($bits({{cpuif.signal("WDATA")}}) == {{ds.package_name}}::{{ds.module_name|upper}}_DATA_WIDTH)
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else $error("WDATA width %0d != DATA_WIDTH %0d",
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$bits({{cpuif.signal("WDATA")}}), {{ds.package_name}}::{{ds.module_name|upper}}_DATA_WIDTH);
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end
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// Simple handshake sanity (one-cycle implication; relax/adjust as needed)
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assert_rd_resp_enc: assert property (@(posedge {{cpuif.signal("ACLK")}})
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{{cpuif.signal("RVALID")}} |-> (^{{cpuif.signal("RRESP")}} !== 1'bx))
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else $error("RRESP must be a legal AXI response when RVALID is high");
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assert_wr_resp_enc: assert property (@(posedge {{cpuif.signal("ACLK")}})
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{{cpuif.signal("BVALID")}} |-> (^{{cpuif.signal("BRESP")}} !== 1'bx))
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else $error("BRESP must be a legal AXI response when BVALID is high");
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`endif
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{% endif -%}
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assign cpuif_req = {{cpuif.signal("AWVALID")}} | {{cpuif.signal("ARVALID")}};
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assign cpuif_wr_en = {{cpuif.signal("AWVALID")}} & {{cpuif.signal("WVALID")}};
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assign cpuif_rd_en = {{cpuif.signal("ARVALID")}};
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assign cpuif_wr_addr = {{cpuif.signal("AWADDR")}};
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assign cpuif_rd_addr = {{cpuif.signal("ARADDR")}};
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assign cpuif_wr_data = {{cpuif.signal("WDATA")}};
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assign cpuif_wr_byte_en = {{cpuif.signal("WSTRB")}};
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//
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// Return paths back to AXI master from generic cpuif_*
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// Read: ack=RVALID, err=RRESP[1] (SLVERR/DECERR), data=RDATA
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//
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assign {{cpuif.signal("RDATA")}} = cpuif_rd_data;
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assign {{cpuif.signal("RVALID")}} = cpuif_rd_ack;
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assign {{cpuif.signal("RRESP")}} = (cpuif_rd_err | cpuif_rd_sel.cpuif_err | cpuif_wr_sel.cpuif_err) ? 2'b10 : 2'b00;
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// Write: ack=BVALID, err=BRESP[1]
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assign {{cpuif.signal("BVALID")}} = cpuif_wr_ack;
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assign {{cpuif.signal("BRESP")}} = (cpuif_wr_err | cpuif_wr_sel.cpuif_err | cpuif_rd_sel.cpuif_err) ? 2'b10 : 2'b00;
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//--------------------------------------------------------------------------
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// Fanout CPU Bus interface signals
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//--------------------------------------------------------------------------
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{{fanout|walk(cpuif=cpuif)}}
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//--------------------------------------------------------------------------
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// Fanin CPU Bus interface signals
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//--------------------------------------------------------------------------
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{{fanin|walk(cpuif=cpuif)}} |