c63b2cbab2
* Downsize paddr bits * Updated Test suite to use offset aligned address * fix for apb3 and axi4lite * modified structure to pass hierarchy information --------- Co-authored-by: Byron Lathi <bslathi19@gmail.com>
91 lines
2.7 KiB
Python
91 lines
2.7 KiB
Python
"""Pytest wrapper launching the APB4 cocotb smoke tests."""
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from __future__ import annotations
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import json
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import logging
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from pathlib import Path
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import logging
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import pytest
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from peakrdl_busdecoder.cpuif.apb4.apb4_cpuif_flat import APB4CpuifFlat
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try: # pragma: no cover - optional dependency shim
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from cocotb.runner import get_runner
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except ImportError: # pragma: no cover
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from cocotb_tools.runner import get_runner
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from tests.cocotb_lib import RDL_CASES
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from tests.cocotb_lib.utils import get_verilog_sources, prepare_cpuif_case, colorize_cocotb_log
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@pytest.mark.simulation
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@pytest.mark.verilator
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@pytest.mark.parametrize(("rdl_file", "top_name"), RDL_CASES, ids=[case[1] for case in RDL_CASES])
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def test_apb4_smoke(tmp_path: Path, rdl_file: str, top_name: str) -> None:
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"""Compile each APB4 design variant and execute the cocotb smoke test."""
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repo_root = Path(__file__).resolve().parents[4]
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rdl_path = repo_root / "tests" / "cocotb_lib" / "rdl" / rdl_file
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build_root = tmp_path / top_name
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logging.info(f"Running APB4 smoke test for {rdl_path} with top {top_name}")
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logging.info(f"Build root: {build_root}")
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module_path, package_path, config = prepare_cpuif_case(
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str(rdl_path),
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top_name,
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build_root,
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cpuif_cls=APB4CpuifFlat,
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control_signal="PSEL",
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)
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sources = get_verilog_sources(
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module_path,
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package_path,
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[repo_root / "hdl-src" / "apb4_intf.sv"],
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)
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runner = get_runner("verilator")
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sim_build = build_root / "sim_build"
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build_log_file = build_root / "build.log"
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sim_log_file = build_root / "simulation.log"
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try:
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runner.build(
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sources=sources,
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hdl_toplevel=module_path.stem,
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build_dir=sim_build,
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log_file=str(build_log_file),
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)
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except SystemExit as e:
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# Print build log on failure for easier debugging
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if build_log_file.exists():
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logging.error(f"""
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=== Build Log ===
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{colorize_cocotb_log(build_log_file.read_text())}
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=== End Build Log ===
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""")
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if e.code != 0:
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raise
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try:
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runner.test(
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hdl_toplevel=module_path.stem,
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test_module="tests.cocotb.apb4.smoke.test_register_access",
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build_dir=sim_build,
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log_file=str(sim_log_file),
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extra_env={"RDL_TEST_CONFIG": json.dumps(config)},
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)
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except SystemExit as e:
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# Print simulation log on failure for easier debugging
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if sim_log_file.exists():
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logging.error(f"""
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=== Simulation Log ===
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{colorize_cocotb_log(sim_log_file.read_text())}
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=== End Simulation Log ===
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""")
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if e.code != 0:
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raise e
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