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Copilot c9addd6ac2 Fix decoder generation for external nested addressable components and add max-decode-depth parameter (#12 )

* Initial plan

* Fix bus decoder to skip external nested components

Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com>

* Optimize external children check using generator expressions

Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com>

* Add max-decode-depth CLI argument

Added --max-decode-depth argument that:
- Is added to CLI arguments in __peakrdl__.py
- Piped into design state via ExporterKwargs and DesignStateKwargs
- Used to control max depth in listener.py
- All 66 tests pass including new test for the parameter

Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com>

---------

Co-authored-by: copilot-swe-agent[bot] <198982749+Copilot@users.noreply.github.com>
Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com>

2025-10-25 19:56:49 -07:00

.github

Add cocotb testbench for validating generated bus decoder RTL across APB3, APB4, and AXI4-Lite interfaces (#9 )

2025-10-23 23:46:51 -07:00

docs

Update documentation to use correct repository name PeakRDL-BusDecoder and clarify project purpose (#7 )

2025-10-23 23:23:10 -07:00

hdl-src

Update documentation to use correct repository name PeakRDL-BusDecoder and clarify project purpose (#7 )

2025-10-23 23:23:10 -07:00

src/peakrdl_busdecoder

Fix decoder generation for external nested addressable components and add max-decode-depth parameter (#12 )

2025-10-25 19:56:49 -07:00

tests

Fix decoder generation for external nested addressable components and add max-decode-depth parameter (#12 )

2025-10-25 19:56:49 -07:00

.gitignore

Fix status checks: lint, format, typecheck, and tests (#8 )

2025-10-23 23:22:09 -07:00

.readthedocs.yaml

Initial Commit - Forked from PeakRDL-regblock @ a440cc19769069be831d267505da4f3789a26695

2025-10-10 22:28:36 -07:00

CONTRIBUTING.md

Update documentation to use correct repository name PeakRDL-BusDecoder and clarify project purpose (#7 )

2025-10-23 23:23:10 -07:00

LICENSE

Initial Commit - Forked from PeakRDL-regblock @ a440cc19769069be831d267505da4f3789a26695

2025-10-10 22:28:36 -07:00

MANIFEST.in

regblock -> busdecoder

2025-10-10 22:30:59 -07:00

pyproject.toml

Add cocotb testbench for validating generated bus decoder RTL across APB3, APB4, and AXI4-Lite interfaces (#9 )

2025-10-23 23:46:51 -07:00

README.md

Update documentation to use correct repository name PeakRDL-BusDecoder and clarify project purpose (#7 )

2025-10-23 23:23:10 -07:00

uv.lock

consolidate common action setup + migrate to ruff and pyrefly

2025-10-13 19:31:39 -07:00

README.md

PeakRDL-BusDecoder

Generate a SystemVerilog bus decoder from SystemRDL that splits CPU interface signals to multiple sub-address spaces. This tool is designed for creating hierarchical register address maps by decoding bus transactions and routing them to the appropriate child address maps.

For the command line tool, see the PeakRDL project.

Documentation

See the PeakRDL-BusDecoder Documentation for more details