* Initial plan * Fix bus decoder to skip external nested components Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Optimize external children check using generator expressions Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Add max-decode-depth CLI argument Added --max-decode-depth argument that: - Is added to CLI arguments in __peakrdl__.py - Piped into design state via ExporterKwargs and DesignStateKwargs - Used to control max depth in listener.py - All 66 tests pass including new test for the parameter Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> --------- Co-authored-by: copilot-swe-agent[bot] <198982749+Copilot@users.noreply.github.com> Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com>
203 lines
6.0 KiB
Python
203 lines
6.0 KiB
Python
"""Test handling of external nested addressable components."""
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from pathlib import Path
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from tempfile import TemporaryDirectory
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import pytest
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from peakrdl_busdecoder import BusDecoderExporter
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from peakrdl_busdecoder.cpuif.apb4 import APB4Cpuif
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@pytest.fixture
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def external_nested_rdl(compile_rdl):
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"""Create an RDL design with external nested addressable components.
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This tests the scenario where an addrmap contains external children
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that themselves have external addressable children.
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The decoder should only generate select signals for the top-level
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external children, not their internal structure.
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"""
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rdl_source = """
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mem queue_t {
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name = "Queue";
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mementries = 1024;
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memwidth = 64;
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};
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addrmap port_t {
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name = "Port";
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desc = "";
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external queue_t common[3] @ 0x0 += 0x2000;
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external queue_t response @ 0x6000;
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};
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addrmap buffer_t {
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name = "Buffer";
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desc = "";
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port_t multicast @ 0x0;
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port_t port [16] @ 0x8000 += 0x8000;
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};
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"""
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return compile_rdl(rdl_source, top="buffer_t")
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@pytest.fixture
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def nested_addrmap_rdl(compile_rdl):
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"""Create an RDL design with nested non-external addrmaps for testing depth control."""
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rdl_source = """
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addrmap level2 {
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reg {
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field { sw=rw; hw=r; } data2[31:0];
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} reg2 @ 0x0;
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reg {
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field { sw=rw; hw=r; } data2b[31:0];
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} reg2b @ 0x4;
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};
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addrmap level1 {
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reg {
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field { sw=rw; hw=r; } data1[31:0];
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} reg1 @ 0x0;
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level2 inner2 @ 0x10;
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};
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addrmap level0 {
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level1 inner1 @ 0x0;
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};
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"""
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return compile_rdl(rdl_source, top="level0")
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def test_external_nested_components_generate_correct_decoder(external_nested_rdl):
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"""Test that external nested components generate correct decoder logic.
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The decoder should:
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- Generate select signals for multicast and port[16]
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- NOT generate select signals for multicast.common[] or multicast.response
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- NOT generate invalid paths like multicast.common[i0]
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"""
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with TemporaryDirectory() as tmpdir:
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exporter = BusDecoderExporter()
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exporter.export(
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external_nested_rdl,
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tmpdir,
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cpuif_cls=APB4Cpuif,
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)
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# Read the generated module
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module_file = Path(tmpdir) / "buffer_t.sv"
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content = module_file.read_text()
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# Should have correct select signals
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assert "cpuif_wr_sel.multicast = 1'b1;" in content
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assert "cpuif_wr_sel.port[i0] = 1'b1;" in content
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# Should NOT have invalid nested paths
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assert "cpuif_wr_sel.multicast.common" not in content
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assert "cpuif_wr_sel.multicast.response" not in content
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assert "cpuif_rd_sel.multicast.common" not in content
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assert "cpuif_rd_sel.multicast.response" not in content
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# Verify struct is flat (no nested structs for external children)
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assert "typedef struct packed" in content
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assert "logic multicast;" in content
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assert "logic [15:0]port;" in content
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def test_external_nested_components_generate_correct_interfaces(external_nested_rdl):
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"""Test that external nested components generate correct interface ports.
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The module should have:
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- One master interface for multicast
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- Array of 16 master interfaces for port[]
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- NO interfaces for internal components like common[] or response
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"""
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with TemporaryDirectory() as tmpdir:
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exporter = BusDecoderExporter()
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exporter.export(
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external_nested_rdl,
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tmpdir,
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cpuif_cls=APB4Cpuif,
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)
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# Read the generated module
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module_file = Path(tmpdir) / "buffer_t.sv"
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content = module_file.read_text()
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# Should have master interfaces for top-level external children
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assert "m_apb_multicast" in content
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assert "m_apb_port [16]" in content or "m_apb_port[16]" in content
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# Should NOT have interfaces for nested external children
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assert "m_apb_multicast_common" not in content
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assert "m_apb_multicast_response" not in content
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assert "m_apb_common" not in content
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assert "m_apb_response" not in content
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def test_non_external_nested_components_are_descended(compile_rdl):
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"""Test that non-external nested components are still descended into.
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This is a regression test to ensure we didn't break normal nested
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component handling.
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"""
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rdl_source = """
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addrmap inner_block {
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reg {
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field {
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sw=rw;
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hw=r;
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} data[31:0];
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} inner_reg @ 0x0;
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};
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addrmap outer_block {
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inner_block inner @ 0x0;
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};
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"""
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top = compile_rdl(rdl_source, top="outer_block")
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with TemporaryDirectory() as tmpdir:
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exporter = BusDecoderExporter()
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exporter.export(top, tmpdir, cpuif_cls=APB4Cpuif)
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# Read the generated module
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module_file = Path(tmpdir) / "outer_block.sv"
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content = module_file.read_text()
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# Should descend into inner and reference inner_reg
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assert "inner" in content
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assert "inner_reg" in content
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def test_max_decode_depth_parameter_exists(compile_rdl):
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"""Test that max_decode_depth parameter can be set."""
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rdl_source = """
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addrmap simple {
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reg {
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field { sw=rw; hw=r; } data[31:0];
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} my_reg @ 0x0;
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};
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"""
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top = compile_rdl(rdl_source, top="simple")
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with TemporaryDirectory() as tmpdir:
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exporter = BusDecoderExporter()
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# Should not raise an exception
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exporter.export(
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top,
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tmpdir,
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cpuif_cls=APB4Cpuif,
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max_decode_depth=2,
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)
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# Verify output was generated
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module_file = Path(tmpdir) / "simple.sv"
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assert module_file.exists()
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