Add workaround to AXI4-Lite cpuif template to avoif quirk in Vivado xsim handling of non-power-of-2 array indexing. #7

2022-05-02 20:51:31 -07:00
parent a1808298ae
commit 03d77ea37b
4 changed files with 15 additions and 2 deletions
--- a/tests/lib/simulators/xilinx.py
+++ b/tests/lib/simulators/xilinx.py
@@ -59,3 +59,5 @@ class Xilinx(Simulator):
                    self.testcase_cls_inst.fail(line)
                elif line.startswith("Fatal:"):
                    self.testcase_cls_inst.fail(line)
+                elif line.startswith("FATAL_ERROR:"):
+                    self.testcase_cls_inst.fail(line)