03d77ea37b14522a258323662b5df309e607fda5
Add workaround to AXI4-Lite cpuif template to avoif quirk in Vivado xsim handling of non-power-of-2 array indexing. #7
PeakRDL-regblock
Compile SystemRDL into a SystemVerilog control/status register (CSR) block
Documentation
See the PeakRDL-regblock Documentation for more details
Description
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