Add workaround to AXI4-Lite cpuif template to avoif quirk in Vivado xsim handling of non-power-of-2 array indexing. #7

src/peakrdl/regblock/cpuif/axi4lite/axi4lite_tmpl.sv

@@ -138,7 +138,14 @@ struct {
     logic is_wr;
     logic err;
     logic [{{cpuif.data_width-1}}:0] rdata;
-} axil_resp_buffer[{{cpuif.resp_buffer_size}}];
+} axil_resp_buffer[{{roundup_pow2(cpuif.resp_buffer_size)}}];
+{%- if not is_pow2(cpuif.resp_buffer_size) %}
+// axil_resp_buffer is intentionally padded to the next power of two despite there
+// only being {{cpuif.resp_buffer_size}} actual entries.
+// This is to avoid quirks in some tools that cannot handle indexing into a non-power-of-2 array.
+// Unused entries are expected to be optimized away
+{% endif %}
+
 logic [{{clog2(cpuif.resp_buffer_size)}}:0] axil_resp_wptr;
 logic [{{clog2(cpuif.resp_buffer_size)}}:0] axil_resp_rptr;
 

src/peakrdl/regblock/cpuif/base.py

@@ -4,7 +4,7 @@ import os
 
 import jinja2 as jj
 
-from ..utils import get_always_ff_event, clog2, is_pow2
+from ..utils import get_always_ff_event, clog2, is_pow2, roundup_pow2
 
 if TYPE_CHECKING:
     from ..exporter import RegblockExporter
@@ -52,6 +52,7 @@ class CpuifBase:
             "get_resetsignal": self.exp.dereferencer.get_resetsignal,
             "clog2": clog2,
             "is_pow2": is_pow2,
+            "roundup_pow2": roundup_pow2,
         }
 
         template = jj_env.get_template(self.template_path)

src/peakrdl/regblock/utils.py

@@ -36,3 +36,6 @@ def clog2(n: int) -> int:
 
 def is_pow2(x: int) -> bool:
     return (x > 0) and ((x & (x - 1)) == 0)
+
+def roundup_pow2(x: int) -> int:
+    return 1<<(x-1).bit_length()

tests/lib/simulators/xilinx.py

@@ -59,3 +59,5 @@ class Xilinx(Simulator):
                     self.testcase_cls_inst.fail(line)
                 elif line.startswith("Fatal:"):
                     self.testcase_cls_inst.fail(line)
+                elif line.startswith("FATAL_ERROR:"):
+                    self.testcase_cls_inst.fail(line)