Doc updates

docs/cpuif/customizing.rst

@@ -1,8 +1,8 @@
 Customizing the CPU interface
 =============================
 
-Bring your own SystemVerilog interface
+Use your own existing SystemVerilog interface definition
---------------------------------------
+--------------------------------------------------------
 
 This exporter comes pre-bundled with its own SystemVerilog interface declarations.
 What if you already have your own SystemVerilog interface declaration that you prefer?
@@ -11,14 +11,15 @@ Not a problem! As long as your interface definition is similar enough, it is eas
 to customize and existing CPUIF definition.
 
 
-The SystemVerilog interface definition bundled with this project for :ref:`cpuif_axi4lite`
+As an example, let's use the SystemVerilog interface definition for
-uses the following style and naming conventions:
+:ref:`cpuif_axi4lite` that is bundled with this project. This interface uses
+ following style and naming conventions:
 
 * SystemVerilog interface type name is ``axi4lite_intf``
 * Defines modports named ``master`` and ``slave``
 * Interface signals are all upper-case: ``AWREADY``, ``AWVALID``, etc...
 
-Lets assume your preferred SV interface uses a slightly different naming convention:
+Lets assume your preferred SV interface definition uses a slightly different naming convention:
 
 * SystemVerilog interface type name is ``axi4_lite_interface``
 * Modports are capitalized and use suffixes ``Master_mp`` and ``Slave_mp``
@@ -33,7 +34,7 @@ Rather than rewriting a new CPU interface definition, you can extend and adjust
     class My_AXI4Lite(AXI4Lite_Cpuif):
         @property
         def port_declaration(self) -> str:
-            # Override the port declaration text to use the alternate type name and modport style
+            # Override the port declaration text to use the alternate interface name and modport style
             return "axi4_lite_interface.Slave_mp s_axil"
 
         def signal(self, name:str) -> str:
@@ -73,4 +74,5 @@ you can define your own.
     Extend your class from :class:`peakrdl_regblock.cpuif.CpuifBase`.
     Define the port declaration string, and provide a reference to your template file.
 
-3. Use your new CPUIF definition when exporting!
+3. Use your new CPUIF definition when exporting.
+4. If you think the CPUIF protocol is something others might find useful, let me know and I can add it to PeakRDL!

docs/props/field.rst

@@ -11,9 +11,13 @@ onread/onwrite
 ^^^^^^^^^^^^^^
 |OK|
 
+All onread/onwrite actions are supported (except for ruser/wuser)
+
 rclr/rset
 ^^^^^^^^^
-See ``onread``
+|OK|
+
+See ``onread``. These are effectively aliases of the onread property.
 
 singlepulse
 ^^^^^^^^^^^
@@ -32,6 +36,7 @@ If set, field will get cleared back to zero after being written.
 sw
 ^^^
 |OK|
+All sw access modes are supported except for ``w1`` and ``rw1``.
 
 swacc
 ^^^^^
@@ -83,8 +88,9 @@ reference
 
 woclr/woset
 ^^^^^^^^^^^
-See ``onwrite``
+|OK|
 
+See ``onwrite``. These are effectively aliases of the onwrite property.
 
 --------------------------------------------------------------------------------
 
@@ -126,6 +132,9 @@ boolean
 reference
     |OK|
 
+    Reference to any single-bit internal object to drive this control.
+
+
 hwenable/hwmask
 ^^^^^^^^^^^^^^^
 |OK|
@@ -157,6 +166,7 @@ boolean
 reference
     |OK|
 
+    Reference to any single-bit internal object to drive this control.
 
 --------------------------------------------------------------------------------
 
@@ -535,8 +545,14 @@ precedence
 ^^^^^^^^^^
 |OK|
 
+Control whether hardware or software has precedence when field value update
+contention occurs. Software has precedence by default.
+
 reset
 ^^^^^
+Control the reset value of the field's storage element.
+If not specified, the field will not be reset.
+
 integer
     |OK|
 
@@ -546,3 +562,5 @@ reference
 resetsignal
 ^^^^^^^^^^^
 |OK|
+
+Provide an alternate reset trigger for this field.

docs/props/reg.rst

@@ -13,3 +13,5 @@ Only ``accesswidth`` that is equal to the ``regwidth`` is supported (default if
 regwidth
 --------
 |OK|
+
+Control the bit-width of the register.