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Allow for write enable and sticky property

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This commit adds new type of fields: sticky with write enable.
This is used to gate status/interrupt register when one or more
interrupts aren't monitored.

Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
This commit is contained in:
Maciej Dudek
2024-04-10 02:14:11 +02:00
committed by Alex Mykyta
parent a7cea87d40
commit 0a9a3ad51e
4 changed files with 423 additions and 45 deletions
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137
tests/test_interrupts/tb_template.sv
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@@ -11,6 +11,8 @@
cpuif.write('h104, 'h000); // ctrl_mask
cpuif.write('h108, 'h1FF); // ctrl_haltenable
cpuif.write('h10C, 'h000); // ctrl_haltmask
cpuif.write('h110, 'h0); // ctrl_we
cpuif.write('h114, 'h3); // ctrl_wel
//--------------------------------------------------------------------------
// Test level_irqs_1
@@ -106,99 +108,154 @@
assert(cb.hwif_out.level_irqs_3.halt == 1'b1);
//--------------------------------------------------------------------------
// Test posedge_irqs
// Test level_irqs with we
cpuif.assert_read('h10, 'h000);
assert(cb.hwif_out.level_irqs_we.intr == 1'b0);
cb.hwif_in.level_irqs_we.irq0.next <= 'h0F;
assert(cb.hwif_in.level_irqs_we.irq0.next == 8'h00);
@cb;
cb.hwif_in.level_irqs_we.irq0.next <= 'h00;
assert(cb.hwif_out.level_irqs_we.intr == 1'b0);
cpuif.assert_read('h10, 'h000);
cpuif.write('h110, 'h1); // enable ctrl_we
@cb;
cpuif.assert_read('h110, 'h1);
assert(cb.hwif_out.level_irqs_we.intr == 1'b0);
cb.hwif_in.level_irqs_we.irq0.next <= 'h0F;
@cb;
assert(cb.hwif_in.level_irqs_we.irq0.next == 8'h0F);
cpuif.assert_read('h10, 'h00F);
assert(cb.hwif_out.level_irqs_we.intr == 1'b1);
cpuif.write('h110, 'h0); // disable ctrl_we
cpuif.write('h10, 'h1FF);
@cb;
assert(cb.hwif_out.level_irqs_we.intr == 1'b0);
cpuif.assert_read('h10, 'h000);
cb.hwif_in.level_irqs_we.irq0.next <= 'h00;
//--------------------------------------------------------------------------
// Test level_irqs with wel
cpuif.assert_read('h14, 'h000);
assert(cb.hwif_out.level_irqs_wel.intr == 1'b0);
cb.hwif_in.level_irqs_wel.irq0.next <= 'h0F;
assert(cb.hwif_in.level_irqs_wel.irq0.next == 8'h00);
@cb;
cb.hwif_in.level_irqs_wel.irq0.next <= 'h00;
cpuif.assert_read('h14, 'h000);
assert(cb.hwif_in.level_irqs_wel.irq0.next == 8'h00);
assert(cb.hwif_out.level_irqs_wel.intr == 1'b0);
cpuif.write('h114, 'h2); // enable ctrl_we
@cb;
cpuif.assert_read('h14, 'h000);
assert(cb.hwif_in.level_irqs_wel.irq0.next == 8'h00);
assert(cb.hwif_out.level_irqs_wel.intr == 1'b0);
cb.hwif_in.level_irqs_wel.irq0.next <= 'h0F;
@cb;
assert(cb.hwif_in.level_irqs_wel.irq0.next == 8'h0F);
cpuif.assert_read('h14, 'h00F);
assert(cb.hwif_out.level_irqs_wel.intr == 1'b1);
cpuif.write('h114, 'h3); // disable ctrl_we
cpuif.write('h14, 'h1FF);
@cb;
assert(cb.hwif_out.level_irqs_wel.intr == 1'b0);
cpuif.assert_read('h14, 'h000);
cb.hwif_in.level_irqs_wel.irq0.next <= 'h00;
//--------------------------------------------------------------------------
// Test posedge_irqs
cpuif.assert_read('h20, 'h000);
assert(cb.hwif_out.posedge_irqs.intr == 1'b0);
cb.hwif_in.posedge_irqs.irq1.next <= 1'b1;
@cb;
cpuif.assert_read('h10, 'h100);
cpuif.assert_read('h20, 'h100);
assert(cb.hwif_out.posedge_irqs.intr == 1'b1);
cpuif.write('h10, 'h100);
cpuif.assert_read('h10, 'h000);
cpuif.write('h20, 'h100);
cpuif.assert_read('h20, 'h000);
assert(cb.hwif_out.posedge_irqs.intr == 1'b0);
cpuif.assert_read('h10, 'h000);
cpuif.assert_read('h20, 'h000);
cb.hwif_in.posedge_irqs.irq1.next <= 1'b0;
cpuif.assert_read('h10, 'h000);
cpuif.assert_read('h20, 'h000);
assert(cb.hwif_out.posedge_irqs.intr == 1'b0);
//--------------------------------------------------------------------------
// Test negedge_irqs
cpuif.assert_read('h20, 'h000);
cpuif.assert_read('h30, 'h000);
assert(cb.hwif_out.negedge_irqs.intr == 1'b0);
cb.hwif_in.negedge_irqs.irq1.next <= 1'b1;
@cb;
cpuif.assert_read('h20, 'h000);
cpuif.assert_read('h30, 'h000);
assert(cb.hwif_out.negedge_irqs.intr == 1'b0);
cb.hwif_in.negedge_irqs.irq1.next <= 1'b0;
cpuif.assert_read('h20, 'h100);
cpuif.assert_read('h30, 'h100);
assert(cb.hwif_out.negedge_irqs.intr == 1'b1);
cpuif.write('h20, 'h100);
cpuif.assert_read('h20, 'h000);
cpuif.write('h30, 'h100);
cpuif.assert_read('h30, 'h000);
assert(cb.hwif_out.negedge_irqs.intr == 1'b0);
cpuif.assert_read('h20, 'h000);
cpuif.assert_read('h30, 'h000);
//--------------------------------------------------------------------------
// Test bothedge_irqs
cpuif.assert_read('h30, 'h000);
cpuif.assert_read('h40, 'h000);
assert(cb.hwif_out.bothedge_irqs.intr == 1'b0);
cb.hwif_in.bothedge_irqs.irq1.next <= 1'b1;
cpuif.assert_read('h30, 'h100);
cpuif.assert_read('h40, 'h100);
assert(cb.hwif_out.bothedge_irqs.intr == 1'b1);
cpuif.write('h30, 'h100);
cpuif.assert_read('h30, 'h000);
cpuif.write('h40, 'h100);
cpuif.assert_read('h40, 'h000);
assert(cb.hwif_out.bothedge_irqs.intr == 1'b0);
cpuif.assert_read('h30, 'h000);
cpuif.assert_read('h40, 'h000);
cb.hwif_in.bothedge_irqs.irq1.next <= 1'b0;
cpuif.assert_read('h30, 'h100);
cpuif.assert_read('h40, 'h100);
assert(cb.hwif_out.bothedge_irqs.intr == 1'b1);
cpuif.write('h30, 'h100);
cpuif.assert_read('h30, 'h000);
cpuif.write('h40, 'h100);
cpuif.assert_read('h40, 'h000);
assert(cb.hwif_out.bothedge_irqs.intr == 1'b0);
cpuif.assert_read('h30, 'h000);
cpuif.assert_read('h40, 'h000);
//--------------------------------------------------------------------------
cpuif.assert_read('h40, 'h000);
// Test top_irq
cpuif.assert_read('h50, 'h000);
assert(cb.hwif_out.top_irq.intr == 1'b0);
cb.hwif_in.level_irqs_1.irq0.next <= 'h01;
@cb;
cb.hwif_in.level_irqs_1.irq0.next <= 'h00;
cpuif.assert_read('h40, 'b0001);
cpuif.assert_read('h50, 'b0001);
assert(cb.hwif_out.top_irq.intr == 1'b1);
cpuif.write('h0, 'h01);
cpuif.assert_read('h40, 'b0000);
cpuif.assert_read('h50, 'b0000);
assert(cb.hwif_out.top_irq.intr == 1'b0);
cb.hwif_in.posedge_irqs.irq0.next <= 'h01;
@cb;
cb.hwif_in.posedge_irqs.irq0.next <= 'h00;
cpuif.assert_read('h40, 'b0010);
cpuif.assert_read('h50, 'b0010);
assert(cb.hwif_out.top_irq.intr == 1'b1);
cpuif.write('h10, 'h01);
cpuif.assert_read('h40, 'b0000);
cpuif.write('h20, 'h01);
cpuif.assert_read('h50, 'b0000);
assert(cb.hwif_out.top_irq.intr == 1'b0);
cb.hwif_in.negedge_irqs.irq0.next <= 'h01;
@cb;
cb.hwif_in.negedge_irqs.irq0.next <= 'h00;
@cb;
cpuif.assert_read('h40, 'b0100);
cpuif.assert_read('h50, 'b0100);
assert(cb.hwif_out.top_irq.intr == 1'b1);
cpuif.write('h20, 'h01);
cpuif.assert_read('h40, 'b0000);
cpuif.write('h30, 'h01);
cpuif.assert_read('h50, 'b0000);
assert(cb.hwif_out.top_irq.intr == 1'b0);
cb.hwif_in.bothedge_irqs.irq0.next <= 'h01;
@cb;
cb.hwif_in.bothedge_irqs.irq0.next <= 'h00;
cpuif.assert_read('h40, 'b1000);
cpuif.assert_read('h50, 'b1000);
assert(cb.hwif_out.top_irq.intr == 1'b1);
cpuif.write('h30, 'h01);
cpuif.assert_read('h40, 'b0000);
cpuif.write('h40, 'h01);
cpuif.assert_read('h50, 'b0000);
assert(cb.hwif_out.top_irq.intr == 1'b0);
cpuif.write('h108, 'h000); // ctrl_haltenable
@@ -206,32 +263,32 @@
@cb;
cb.hwif_in.level_irqs_2.irq0.next <= 'h00;
@cb;
cpuif.assert_read('h40, 'b00000);
cpuif.assert_read('h50, 'b00000);
assert(cb.hwif_out.top_irq.intr == 1'b0);
cpuif.write('h108, 'h001); // ctrl_haltenable
cpuif.assert_read('h40, 'b10000);
cpuif.assert_read('h50, 'b10000);
assert(cb.hwif_out.top_irq.intr == 1'b1);
cpuif.write('h4, 'h01);
cpuif.assert_read('h40, 'b00000);
cpuif.assert_read('h50, 'b00000);
assert(cb.hwif_out.top_irq.intr == 1'b0);
//--------------------------------------------------------------------------
// Test multi-bit sticky reg
cpuif.assert_read('h50, 'h00);
cpuif.assert_read('h60, 'h00);
cb.hwif_in.stickyreg.stickyfield.next <= 'h12;
@cb;
cb.hwif_in.stickyreg.stickyfield.next <= 'h34;
@cb;
cb.hwif_in.stickyreg.stickyfield.next <= 'h56;
@cb;
cpuif.assert_read('h50, 'h12);
cpuif.write('h50, 'h00);
cpuif.assert_read('h60, 'h12);
cpuif.write('h60, 'h00);
@cb;
cb.hwif_in.stickyreg.stickyfield.next <= 'h78;
@cb;
cpuif.assert_read('h50, 'h56);
cpuif.assert_read('h60, 'h56);
{% endblock %}