bslathi19/PeakRDL-regblock
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Remove unreachable code

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According to the SystemRDL specification interrupt can be either:
level, posedge, negedge, bothedge, or nonsticky.
This means that it's impossible to reach create filed that
satisfies [Pos|Neg|Both]edgeNonstickybit match functions.

Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
This commit is contained in:
Maciej Dudek
2024-04-09 23:14:17 +02:00
committed by Alex Mykyta
parent 4aed443c55
commit a7cea87d40
2 changed files with 1 additions and 67 deletions
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3
src/peakrdl_regblock/field_logic/__init__.py
View File

@@ -447,9 +447,6 @@ class FieldLogic:
self.add_hw_conditional(hw_interrupts.PosedgeStickybit(self.exp), AssignmentPrecedence.HW_WRITE)
self.add_hw_conditional(hw_interrupts.NegedgeStickybit(self.exp), AssignmentPrecedence.HW_WRITE)
self.add_hw_conditional(hw_interrupts.BothedgeStickybit(self.exp), AssignmentPrecedence.HW_WRITE)
self.add_hw_conditional(hw_interrupts.PosedgeNonsticky(self.exp), AssignmentPrecedence.HW_WRITE)
self.add_hw_conditional(hw_interrupts.NegedgeNonsticky(self.exp), AssignmentPrecedence.HW_WRITE)
self.add_hw_conditional(hw_interrupts.BothedgeNonsticky(self.exp), AssignmentPrecedence.HW_WRITE)
self.add_hw_conditional(hw_interrupts.Sticky(self.exp), AssignmentPrecedence.HW_WRITE)
self.add_hw_conditional(hw_interrupts.Stickybit(self.exp), AssignmentPrecedence.HW_WRITE)
self.add_hw_conditional(hw_write.WEWrite(self.exp), AssignmentPrecedence.HW_WRITE)

65
src/peakrdl_regblock/field_logic/hw_interrupts.py
View File

@@ -2,7 +2,7 @@ from typing import TYPE_CHECKING, List
from systemrdl.rdltypes import InterruptType
from .bases import NextStateConditional, NextStateUnconditional
from .bases import NextStateConditional
if TYPE_CHECKING:
from systemrdl.node import FieldNode
@@ -160,66 +160,3 @@ class BothedgeStickybit(NextStateConditional):
f"next_c = {R} | ({Iq} ^ {I});",
"load_next_c = '1;",
]
class PosedgeNonsticky(NextStateUnconditional):
"""
Positive edge non-stickybit
"""
comment = "posedge nonsticky"
unconditional_explanation = "Edge-sensitive non-sticky interrupts always update the field state"
def is_match(self, field: 'FieldNode') -> bool:
return (
field.is_hw_writable
and not field.get_property('stickybit')
and field.get_property('intr type') == InterruptType.posedge
)
def get_assignments(self, field: 'FieldNode') -> List[str]:
I = self.exp.hwif.get_input_identifier(field)
Iq = self.exp.field_logic.get_next_q_identifier(field)
return [
f"next_c = ~{Iq} & {I};",
"load_next_c = '1;",
]
class NegedgeNonsticky(NextStateUnconditional):
"""
Negative edge non-stickybit
"""
comment = "negedge nonsticky"
unconditional_explanation = "Edge-sensitive non-sticky interrupts always update the field state"
def is_match(self, field: 'FieldNode') -> bool:
return (
field.is_hw_writable
and not field.get_property('stickybit')
and field.get_property('intr type') == InterruptType.negedge
)
def get_assignments(self, field: 'FieldNode') -> List[str]:
I = self.exp.hwif.get_input_identifier(field)
Iq = self.exp.field_logic.get_next_q_identifier(field)
return [
f"next_c = {Iq} & ~{I};",
"load_next_c = '1;",
]
class BothedgeNonsticky(NextStateUnconditional):
"""
edge-sensitive non-stickybit
"""
comment = "bothedge nonsticky"
unconditional_explanation = "Edge-sensitive non-sticky interrupts always update the field state"
def is_match(self, field: 'FieldNode') -> bool:
return (
field.is_hw_writable
and not field.get_property('stickybit')
and field.get_property('intr type') == InterruptType.bothedge
)
def get_assignments(self, field: 'FieldNode') -> List[str]:
I = self.exp.hwif.get_input_identifier(field)
Iq = self.exp.field_logic.get_next_q_identifier(field)
return [
f"next_c = {Iq} ^ {I};",
"load_next_c = '1;",
]