don't emit write/read-buffer logic for external components

This commit is contained in:
Dana Sorensen
2025-10-23 20:37:27 -06:00
committed by Alex Mykyta
parent 087b1f8611
commit 18cf2aabc7
5 changed files with 8 additions and 6 deletions

View File

@@ -22,7 +22,7 @@ class RBufLogicGenerator(RDLForLoopGenerator):
super().enter_Reg(node)
assert isinstance(node.inst, Reg)
if not node.get_property('buffer_reads'):
if not node.get_property('buffer_reads') or node.external:
return
context = {

View File

@@ -11,7 +11,7 @@ class RBufStorageStructGenerator(RDLStructGenerator):
def enter_Reg(self, node: RegNode) -> None:
super().enter_Reg(node)
if not node.get_property('buffer_reads'):
if not node.get_property('buffer_reads') or node.external:
return
regwidth = node.get_property('regwidth')

View File

@@ -95,8 +95,10 @@ class DesignScanner(RDLListener):
accesswidth = node.get_property('accesswidth')
self.ds.cpuif_data_width = max(self.ds.cpuif_data_width, accesswidth)
self.ds.has_buffered_write_regs = self.ds.has_buffered_write_regs or bool(node.get_property('buffer_writes'))
self.ds.has_buffered_read_regs = self.ds.has_buffered_read_regs or bool(node.get_property('buffer_reads'))
if node.get_property('buffer_writes') and not node.external:
self.ds.has_buffered_write_regs = True
if node.get_property('buffer_reads') and not node.external:
self.ds.has_buffered_read_regs = True
def enter_Signal(self, node: 'SignalNode') -> None:
if node.get_property('field_reset'):

View File

@@ -23,7 +23,7 @@ class WBufLogicGenerator(RDLForLoopGenerator):
super().enter_Reg(node)
assert isinstance(node.inst, Reg)
if not node.get_property('buffer_writes'):
if not node.get_property('buffer_writes') or node.external:
return
regwidth = node.get_property('regwidth')

View File

@@ -19,7 +19,7 @@ class WBufStorageStructGenerator(RDLStructGenerator):
def enter_Reg(self, node: RegNode) -> None:
super().enter_Reg(node)
if not node.get_property('buffer_writes'):
if not node.get_property('buffer_writes') or node.external:
return
regwidth = node.get_property('regwidth')