bslathi19/PeakRDL-regblock
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

don't emit write/read-buffer logic for external components

Browse Source
This commit is contained in:
Dana Sorensen
2025-10-23 20:37:27 -06:00
committed by Alex Mykyta
parent 087b1f8611
commit 18cf2aabc7
5 changed files with 8 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/peakrdl_regblock/read_buffering/implementation_generator.py
View File

@@ -22,7 +22,7 @@ class RBufLogicGenerator(RDLForLoopGenerator):
super().enter_Reg(node) super().enter_Reg(node)
assert isinstance(node.inst, Reg) assert isinstance(node.inst, Reg)
if not node.get_property('buffer_reads'): if not node.get_property('buffer_reads') or node.external:
return return
context = { context = {

2
src/peakrdl_regblock/read_buffering/storage_generator.py
View File

@@ -11,7 +11,7 @@ class RBufStorageStructGenerator(RDLStructGenerator):
def enter_Reg(self, node: RegNode) -> None: def enter_Reg(self, node: RegNode) -> None:
super().enter_Reg(node) super().enter_Reg(node)
if not node.get_property('buffer_reads'): if not node.get_property('buffer_reads') or node.external:
return return
regwidth = node.get_property('regwidth') regwidth = node.get_property('regwidth')

6
src/peakrdl_regblock/scan_design.py
View File

@@ -95,8 +95,10 @@ class DesignScanner(RDLListener):
accesswidth = node.get_property('accesswidth') accesswidth = node.get_property('accesswidth')
self.ds.cpuif_data_width = max(self.ds.cpuif_data_width, accesswidth) self.ds.cpuif_data_width = max(self.ds.cpuif_data_width, accesswidth)
self.ds.has_buffered_write_regs = self.ds.has_buffered_write_regs or bool(node.get_property('buffer_writes')) if node.get_property('buffer_writes') and not node.external:
self.ds.has_buffered_read_regs = self.ds.has_buffered_read_regs or bool(node.get_property('buffer_reads')) self.ds.has_buffered_write_regs = True
if node.get_property('buffer_reads') and not node.external:
self.ds.has_buffered_read_regs = True
def enter_Signal(self, node: 'SignalNode') -> None: def enter_Signal(self, node: 'SignalNode') -> None:
if node.get_property('field_reset'): if node.get_property('field_reset'):

2
src/peakrdl_regblock/write_buffering/implementation_generator.py
View File

@@ -23,7 +23,7 @@ class WBufLogicGenerator(RDLForLoopGenerator):
super().enter_Reg(node) super().enter_Reg(node)
assert isinstance(node.inst, Reg) assert isinstance(node.inst, Reg)
if not node.get_property('buffer_writes'): if not node.get_property('buffer_writes') or node.external:
return return
regwidth = node.get_property('regwidth') regwidth = node.get_property('regwidth')

2
src/peakrdl_regblock/write_buffering/storage_generator.py
View File

@@ -19,7 +19,7 @@ class WBufStorageStructGenerator(RDLStructGenerator):
def enter_Reg(self, node: RegNode) -> None: def enter_Reg(self, node: RegNode) -> None:
super().enter_Reg(node) super().enter_Reg(node)
if not node.get_property('buffer_writes'): if not node.get_property('buffer_writes') or node.external:
return return
regwidth = node.get_property('regwidth') regwidth = node.get_property('regwidth')