bslathi19/PeakRDL-regblock
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Make stickybit conditional predicate a single-bit result rather than a vector. #54

Browse Source
This commit is contained in:
Alex Mykyta
2023-07-18 21:50:51 -07:00
parent df5436f765
commit 18f8f358b2
1 changed files with 1 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/peakrdl_regblock/field_logic/hw_interrupts.py
View File

@@ -121,7 +121,7 @@ class BothedgeStickybit(NextStateConditional):
def get_predicate(self, field: 'FieldNode') -> str: def get_predicate(self, field: 'FieldNode') -> str:
I = self.exp.hwif.get_input_identifier(field) I = self.exp.hwif.get_input_identifier(field)
Iq = self.exp.field_logic.get_next_q_identifier(field) Iq = self.exp.field_logic.get_next_q_identifier(field)
return f"{Iq} ^ {I}" return f"{Iq} != {I}"
def get_assignments(self, field: 'FieldNode') -> List[str]: def get_assignments(self, field: 'FieldNode') -> List[str]:
I = self.exp.hwif.get_input_identifier(field) I = self.exp.hwif.get_input_identifier(field)