bslathi19/PeakRDL-regblock
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Alex Mykyta
2022-03-20 23:00:31 -07:00
parent de09f07450
commit 19edc135e3
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docs/index.rst
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@@ -2,7 +2,7 @@ Introduction
============ ============
PeakRDL-regblock is a free and open-source control & status register (CSR) compiler. PeakRDL-regblock is a free and open-source control & status register (CSR) compiler.
This code generator that will translate your SystemRDL register description into This code generator translates your SystemRDL register description into
a synthesizable SystemVerilog RTL module that can be easily instantiated into a synthesizable SystemVerilog RTL module that can be easily instantiated into
your hardware design. your hardware design.