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Move SV interface files into a common location. Add license info (#20)

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Alex Mykyta
2022-09-27 20:52:06 -07:00
parent 6fa5031ada
commit 1aa9d8b603
11 changed files with 19 additions and 41 deletions
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4
docs/cpuif/apb.rst
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@@ -29,7 +29,7 @@ The APB3 CPU interface comes in two i/o port flavors:
SystemVerilog Interface
Class: :class:`peakrdl_regblock.cpuif.apb3.APB3_Cpuif`
Interface Definition: :download:`apb3_intf.sv <../../tests/lib/cpuifs/apb3/apb3_intf.sv>`
Interface Definition: :download:`apb3_intf.sv <../../hdl-src/apb3_intf.sv>`
Flattened inputs/outputs
Flattens the interface into discrete input and output ports.
@@ -49,7 +49,7 @@ The APB4 CPU interface comes in two i/o port flavors:
SystemVerilog Interface
Class: :class:`peakrdl_regblock.cpuif.apb4.APB4_Cpuif`
Interface Definition: :download:`apb4_intf.sv <../../tests/lib/cpuifs/apb4/apb4_intf.sv>`
Interface Definition: :download:`apb4_intf.sv <../../hdl-src/apb4_intf.sv>`
Flattened inputs/outputs
Flattens the interface into discrete input and output ports.

31
docs/cpuif/apb4.rst
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@@ -1,31 +0,0 @@
AMBA 4 APB
==========
Implements the register block using an
`AMBA 4 APB <https://developer.arm.com/documentation/ihi0024/d/?lang=en>`_
CPU interface.
The APB4 CPU interface comes in two i/o port flavors:
SystemVerilog Interface
Class: :class:`peakrdl_regblock.cpuif.apb4.APB4_Cpuif`
Interface Definition: :download:`apb4_intf.sv <../../tests/lib/cpuifs/apb4/apb4_intf.sv>`
Flattened inputs/outputs
Flattens the interface into discrete input and output ports.
Class: :class:`peakrdl_regblock.cpuif.apb4.APB4_Cpuif_flattened`
.. warning::
Some IP vendors will incorrectly implement the address signalling
assuming word-addresses. (that each increment of ``PADDR`` is the next word)
For this exporter, values on the interface's ``PADDR`` input are interpreted
as byte-addresses. (a 32-bit APB bus increments ``PADDR`` in steps of 4)
Although APB protocol does not allow for unaligned transfers, this is in
accordance to the official AMBA bus specification.
Be sure to double-check the interpretation of your interconnect IP. A simple
bit-shift operation can be used to correct this if necessary.

2
docs/cpuif/axi4lite.rst
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@@ -12,7 +12,7 @@ The AXI4-Lite CPU interface comes in two i/o port flavors:
SystemVerilog Interface
Class: :class:`peakrdl_regblock.cpuif.axi4lite.AXI4Lite_Cpuif`
Interface Definition: :download:`axi4lite_intf.sv <../../tests/lib/cpuifs/axi4lite/axi4lite_intf.sv>`
Interface Definition: :download:`axi4lite_intf.sv <../../hdl-src/axi4lite_intf.sv>`
Flattened inputs/outputs
Flattens the interface into discrete input and output ports.

2
docs/cpuif/customizing.rst
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@@ -13,7 +13,7 @@ to customize and existing CPUIF definition.
As an example, let's use the SystemVerilog interface definition for
:ref:`cpuif_axi4lite` that is bundled with this project. This interface uses
following style and naming conventions:
the following style and naming conventions:
* SystemVerilog interface type name is ``axi4lite_intf``
* Defines modports named ``master`` and ``slave``