Move SV interface files into a common location. Add license info (#20)

2022-09-27 20:52:06 -07:00
parent 6fa5031ada
commit 1aa9d8b603
11 changed files with 19 additions and 41 deletions
--- a/docs/cpuif/axi4lite.rst
+++ b/docs/cpuif/axi4lite.rst
@@ -12,7 +12,7 @@ The AXI4-Lite CPU interface comes in two i/o port flavors:
 SystemVerilog Interface
    Class: :class:`peakrdl_regblock.cpuif.axi4lite.AXI4Lite_Cpuif`

-    Interface Definition: :download:`axi4lite_intf.sv <../../tests/lib/cpuifs/axi4lite/axi4lite_intf.sv>`
+    Interface Definition: :download:`axi4lite_intf.sv <../../hdl-src/axi4lite_intf.sv>`

 Flattened inputs/outputs
    Flattens the interface into discrete input and output ports.