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Move SV interface files into a common location. Add license info (#20)

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Alex Mykyta
2022-09-27 20:52:06 -07:00
parent 6fa5031ada
commit 1aa9d8b603
11 changed files with 19 additions and 41 deletions
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docs/cpuif/customizing.rst
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@@ -13,7 +13,7 @@ to customize and existing CPUIF definition.
As an example, let's use the SystemVerilog interface definition for
:ref:`cpuif_axi4lite` that is bundled with this project. This interface uses
following style and naming conventions:
the following style and naming conventions:
* SystemVerilog interface type name is ``axi4lite_intf``
* Defines modports named ``master`` and ``slave``