bslathi19/PeakRDL-regblock
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Move SV interface files into a common location. Add license info (#20)

Browse Source
This commit is contained in:
Alex Mykyta
2022-09-27 20:52:06 -07:00
parent 6fa5031ada
commit 1aa9d8b603
11 changed files with 19 additions and 41 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
tests/lib/cpuifs/apb3/__init__.py
View File

@@ -5,10 +5,10 @@ from peakrdl_regblock.cpuif.apb3 import APB3_Cpuif, APB3_Cpuif_flattened
class APB3(CpuifTestMode):
cpuif_cls = APB3_Cpuif
rtl_files = [
"apb3_intf.sv",
"../../../../hdl-src/apb3_intf.sv",
]
tb_files = [
"apb3_intf.sv",
"../../../../hdl-src/apb3_intf.sv",
"apb3_intf_driver.sv",
]
tb_template = "tb_inst.sv"

40
tests/lib/cpuifs/apb3/apb3_intf.sv
View File

@@ -1,40 +0,0 @@
interface apb3_intf #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 32
);
// Command
logic PSEL;
logic PENABLE;
logic PWRITE;
logic [ADDR_WIDTH-1:0] PADDR;
logic [DATA_WIDTH-1:0] PWDATA;
// Response
logic [DATA_WIDTH-1:0] PRDATA;
logic PREADY;
logic PSLVERR;
modport master (
output PSEL,
output PENABLE,
output PWRITE,
output PADDR,
output PWDATA,
input PRDATA,
input PREADY,
input PSLVERR
);
modport slave (
input PSEL,
input PENABLE,
input PWRITE,
input PADDR,
input PWDATA,
output PRDATA,
output PREADY,
output PSLVERR
);
endinterface

4
tests/lib/cpuifs/apb4/__init__.py
View File

@@ -5,10 +5,10 @@ from peakrdl_regblock.cpuif.apb4 import APB4_Cpuif, APB4_Cpuif_flattened
class APB4(CpuifTestMode):
cpuif_cls = APB4_Cpuif
rtl_files = [
"apb4_intf.sv",
"../../../../hdl-src/apb4_intf.sv",
]
tb_files = [
"apb4_intf.sv",
"../../../../hdl-src/apb4_intf.sv",
"apb4_intf_driver.sv",
]
tb_template = "tb_inst.sv"

46
tests/lib/cpuifs/apb4/apb4_intf.sv
View File

@@ -1,46 +0,0 @@
interface apb4_intf #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 32
);
// Command
logic PSEL;
logic PENABLE;
logic PWRITE;
logic [2:0] PPROT;
logic [ADDR_WIDTH-1:0] PADDR;
logic [DATA_WIDTH-1:0] PWDATA;
logic [DATA_WIDTH/8-1:0] PSTRB;
// Response
logic [DATA_WIDTH-1:0] PRDATA;
logic PREADY;
logic PSLVERR;
modport master (
output PSEL,
output PENABLE,
output PWRITE,
output PPROT,
output PADDR,
output PWDATA,
output PSTRB,
input PRDATA,
input PREADY,
input PSLVERR
);
modport slave (
input PSEL,
input PENABLE,
input PWRITE,
input PPROT,
input PADDR,
input PWDATA,
input PSTRB,
output PRDATA,
output PREADY,
output PSLVERR
);
endinterface

4
tests/lib/cpuifs/axi4lite/__init__.py
View File

@@ -5,10 +5,10 @@ from peakrdl_regblock.cpuif.axi4lite import AXI4Lite_Cpuif, AXI4Lite_Cpuif_flatt
class AXI4Lite(CpuifTestMode):
cpuif_cls = AXI4Lite_Cpuif
rtl_files = [
"axi4lite_intf.sv",
"../../../../hdl-src/axi4lite_intf.sv",
]
tb_files = [
"axi4lite_intf.sv",
"../../../../hdl-src/axi4lite_intf.sv",
"axi4lite_intf_driver.sv",
]
tb_template = "tb_inst.sv"

80
tests/lib/cpuifs/axi4lite/axi4lite_intf.sv
View File

@@ -1,80 +0,0 @@
interface axi4lite_intf #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 32
);
logic AWREADY;
logic AWVALID;
logic [ADDR_WIDTH-1:0] AWADDR;
logic [2:0] AWPROT;
logic WREADY;
logic WVALID;
logic [DATA_WIDTH-1:0] WDATA;
logic [DATA_WIDTH/8-1:0] WSTRB;
logic BREADY;
logic BVALID;
logic [1:0] BRESP;
logic ARREADY;
logic ARVALID;
logic [ADDR_WIDTH-1:0] ARADDR;
logic [2:0] ARPROT;
logic RREADY;
logic RVALID;
logic [DATA_WIDTH-1:0] RDATA;
logic [1:0] RRESP;
modport master (
input AWREADY,
output AWVALID,
output AWADDR,
output AWPROT,
input WREADY,
output WVALID,
output WDATA,
output WSTRB,
output BREADY,
input BVALID,
input BRESP,
input ARREADY,
output ARVALID,
output ARADDR,
output ARPROT,
output RREADY,
input RVALID,
input RDATA,
input RRESP
);
modport slave (
output AWREADY,
input AWVALID,
input AWADDR,
input AWPROT,
output WREADY,
input WVALID,
input WDATA,
input WSTRB,
input BREADY,
output BVALID,
output BRESP,
output ARREADY,
input ARVALID,
input ARADDR,
input ARPROT,
input RREADY,
output RVALID,
output RDATA,
output RRESP
);
endinterface