Move SV interface files into a common location. Add license info (#20)

docs/cpuif/apb.rst

@@ -29,7 +29,7 @@ The APB3 CPU interface comes in two i/o port flavors:
 SystemVerilog Interface
     Class: :class:`peakrdl_regblock.cpuif.apb3.APB3_Cpuif`
 
-    Interface Definition: :download:`apb3_intf.sv <../../tests/lib/cpuifs/apb3/apb3_intf.sv>`
+    Interface Definition: :download:`apb3_intf.sv <../../hdl-src/apb3_intf.sv>`
 
 Flattened inputs/outputs
     Flattens the interface into discrete input and output ports.
@@ -49,7 +49,7 @@ The APB4 CPU interface comes in two i/o port flavors:
 SystemVerilog Interface
     Class: :class:`peakrdl_regblock.cpuif.apb4.APB4_Cpuif`
 
-    Interface Definition: :download:`apb4_intf.sv <../../tests/lib/cpuifs/apb4/apb4_intf.sv>`
+    Interface Definition: :download:`apb4_intf.sv <../../hdl-src/apb4_intf.sv>`
 
 Flattened inputs/outputs
     Flattens the interface into discrete input and output ports.

docs/cpuif/apb4.rst

@@ -1,31 +0,0 @@
-AMBA 4 APB
-==========
-
-Implements the register block using an
-`AMBA 4 APB <https://developer.arm.com/documentation/ihi0024/d/?lang=en>`_
-CPU interface.
-
-The APB4 CPU interface comes in two i/o port flavors:
-
-SystemVerilog Interface
-    Class: :class:`peakrdl_regblock.cpuif.apb4.APB4_Cpuif`
-
-    Interface Definition: :download:`apb4_intf.sv <../../tests/lib/cpuifs/apb4/apb4_intf.sv>`
-
-Flattened inputs/outputs
-    Flattens the interface into discrete input and output ports.
-
-    Class: :class:`peakrdl_regblock.cpuif.apb4.APB4_Cpuif_flattened`
-
-
-.. warning::
-    Some IP vendors will incorrectly implement the address signalling
-    assuming word-addresses. (that each increment of ``PADDR`` is the next word)
-
-    For this exporter, values on the interface's ``PADDR`` input are interpreted
-    as byte-addresses. (a 32-bit APB bus increments ``PADDR`` in steps of 4)
-    Although APB protocol does not allow for unaligned transfers, this is in
-    accordance to the official AMBA bus specification.
-
-    Be sure to double-check the interpretation of your interconnect IP. A simple
-    bit-shift operation can be used to correct this if necessary.

docs/cpuif/axi4lite.rst

@@ -12,7 +12,7 @@ The AXI4-Lite CPU interface comes in two i/o port flavors:
 SystemVerilog Interface
     Class: :class:`peakrdl_regblock.cpuif.axi4lite.AXI4Lite_Cpuif`
 
-    Interface Definition: :download:`axi4lite_intf.sv <../../tests/lib/cpuifs/axi4lite/axi4lite_intf.sv>`
+    Interface Definition: :download:`axi4lite_intf.sv <../../hdl-src/axi4lite_intf.sv>`
 
 Flattened inputs/outputs
     Flattens the interface into discrete input and output ports.

docs/cpuif/customizing.rst

@@ -13,7 +13,7 @@ to customize and existing CPUIF definition.
 
 As an example, let's use the SystemVerilog interface definition for
 :ref:`cpuif_axi4lite` that is bundled with this project. This interface uses
- following style and naming conventions:
+the following style and naming conventions:
 
 * SystemVerilog interface type name is ``axi4lite_intf``
 * Defines modports named ``master`` and ``slave``

hdl-src/README.md

@@ -0,0 +1,9 @@
+# HDL Source Files
+This folder contains some SystemVerilog definitions that are useful collateral
+to be used alongside this project.
+
+These reference files are free to use for any purpose and are not covered by
+this project's GPLv3 license.
+
+If for whatever reason you feel the need to reference a license when using
+these, then lets go with the [MIT License](https://choosealicense.com/licenses/mit/)

tests/lib/cpuifs/apb3/__init__.py

@@ -5,10 +5,10 @@ from peakrdl_regblock.cpuif.apb3 import APB3_Cpuif, APB3_Cpuif_flattened
 class APB3(CpuifTestMode):
     cpuif_cls = APB3_Cpuif
     rtl_files = [
-        "apb3_intf.sv",
+        "../../../../hdl-src/apb3_intf.sv",
     ]
     tb_files = [
-        "apb3_intf.sv",
+        "../../../../hdl-src/apb3_intf.sv",
         "apb3_intf_driver.sv",
     ]
     tb_template = "tb_inst.sv"

tests/lib/cpuifs/apb4/__init__.py

@@ -5,10 +5,10 @@ from peakrdl_regblock.cpuif.apb4 import APB4_Cpuif, APB4_Cpuif_flattened
 class APB4(CpuifTestMode):
     cpuif_cls = APB4_Cpuif
     rtl_files = [
-        "apb4_intf.sv",
+        "../../../../hdl-src/apb4_intf.sv",
     ]
     tb_files = [
-        "apb4_intf.sv",
+        "../../../../hdl-src/apb4_intf.sv",
         "apb4_intf_driver.sv",
     ]
     tb_template = "tb_inst.sv"

tests/lib/cpuifs/axi4lite/__init__.py

@@ -5,10 +5,10 @@ from peakrdl_regblock.cpuif.axi4lite import AXI4Lite_Cpuif, AXI4Lite_Cpuif_flatt
 class AXI4Lite(CpuifTestMode):
     cpuif_cls = AXI4Lite_Cpuif
     rtl_files = [
-        "axi4lite_intf.sv",
+        "../../../../hdl-src/axi4lite_intf.sv",
     ]
     tb_files = [
-        "axi4lite_intf.sv",
+        "../../../../hdl-src/axi4lite_intf.sv",
         "axi4lite_intf_driver.sv",
     ]
     tb_template = "tb_inst.sv"