First read/write!

test/.gitignore

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+work
+transcript
+*.wlf

test/drivers/apb3_intf_driver.sv

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+interface apb3_intf_driver #(
+        parameter DATA_WIDTH = 32,
+        parameter ADDR_WIDTH = 32
+    )(
+        input wire clk,
+        apb3_intf.master m_apb
+    );
+
+    timeunit 1ps;
+    timeprecision 1ps;
+
+    logic PSEL;
+    logic PENABLE;
+    logic PWRITE;
+    logic [ADDR_WIDTH-1:0] PADDR;
+    logic [DATA_WIDTH-1:0] PWDATA;
+    logic [DATA_WIDTH-1:0] PRDATA;
+    logic PREADY;
+    logic PSLVERR;
+
+    assign m_apb.PSEL = PSEL;
+    assign m_apb.PENABLE = PENABLE;
+    assign m_apb.PWRITE = PWRITE;
+    assign m_apb.PADDR = PADDR;
+    assign m_apb.PWDATA = PWDATA;
+    assign PRDATA = m_apb.PRDATA;
+    assign PREADY = m_apb.PREADY;
+    assign PSLVERR = m_apb.PSLVERR;
+
+    default clocking cb @(posedge clk);
+        default input #1step output #1;
+        output PSEL;
+        output PENABLE;
+        output PWRITE;
+        output PADDR;
+        output PWDATA;
+        input PRDATA;
+        input PREADY;
+        input PSLVERR;
+    endclocking
+
+    task reset();
+        cb.PSEL <= '0;
+        cb.PENABLE <= '0;
+        cb.PWRITE <= '0;
+        cb.PADDR <= '0;
+        cb.PWDATA <= '0;
+    endtask
+
+    task write(logic [ADDR_WIDTH-1:0] addr, logic [DATA_WIDTH-1:0] data);
+        ##0;
+
+        // Initiate transfer
+        cb.PSEL <= '1;
+        cb.PENABLE <= '0;
+        cb.PWRITE <= '1;
+        cb.PADDR <= addr;
+        cb.PWDATA <= data;
+        @(cb);
+
+        // active phase
+        cb.PENABLE <= '1;
+        @(cb);
+
+        // Wait for response
+        while(cb.PREADY !== 1'b1) @(cb);
+        reset();
+    endtask
+
+    task read(logic [ADDR_WIDTH-1:0] addr, output logic [DATA_WIDTH-1:0] data);
+        ##0;
+
+        // Initiate transfer
+        cb.PSEL <= '1;
+        cb.PENABLE <= '0;
+        cb.PWRITE <= '0;
+        cb.PADDR <= addr;
+        cb.PWDATA <= '0;
+        @(cb);
+
+        // active phase
+        cb.PENABLE <= '1;
+        @(cb);
+
+        // Wait for response
+        while(cb.PREADY !== 1'b1) @(cb);
+        data = cb.PRDATA;
+        reset();
+    endtask
+
+    initial begin
+        reset();
+    end
+
+endinterface

test/interfaces/apb3_intf.sv

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+interface apb3_intf #(
+    parameter DATA_WIDTH = 32,
+    parameter ADDR_WIDTH = 32
+);
+    // Command
+    logic PSEL;
+    logic PENABLE;
+    logic PWRITE;
+    logic [ADDR_WIDTH-1:0] PADDR;
+    logic [DATA_WIDTH-1:0] PWDATA;
+
+    // Response
+    logic [DATA_WIDTH-1:0] PRDATA;
+    logic PREADY;
+    logic PSLVERR;
+
+    modport master (
+        output PSEL,
+        output PENABLE,
+        output PWRITE,
+        output PADDR,
+        output PWDATA,
+
+        input PRDATA,
+        input PREADY,
+        input PSLVERR
+    );
+
+    modport slave (
+        input PSEL,
+        input PENABLE,
+        input PWRITE,
+        input PADDR,
+        input PWDATA,
+
+        output PRDATA,
+        output PREADY,
+        output PSLVERR
+    );
+endinterface

test/run.sh

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+#!/bin/bash
+set -e
+
+../export.py test_regblock.rdl
+
+vlog -sv -suppress 2720 -quiet -f src.f
+vsim -c -quiet tb -do "log -r /*; run -all; exit;"

test/src.f

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+interfaces/apb3_intf.sv
+drivers/apb3_intf_driver.sv
+test_regblock_pkg.sv
+test_regblock.sv
+tb.sv

test/tb.sv

@@ -0,0 +1,51 @@
+module tb;
+    timeunit 1ns;
+    timeprecision 1ps;
+
+    logic rst = '1;
+    logic clk = '0;
+    initial forever begin
+        #10ns;
+        clk = ~clk;
+    end
+
+    apb3_intf apb();
+
+    apb3_intf_driver driver(
+        .clk(clk),
+        .m_apb(apb)
+    );
+
+
+    test_regblock dut (
+        .clk(clk),
+        .rst(rst),
+        .s_apb(apb),
+        .hwif_out()
+    );
+
+
+    initial begin
+        logic [31:0] rd_data;
+
+        repeat(5) @(posedge clk);
+        rst = '0;
+        repeat(5) @(posedge clk);
+
+        driver.read('h000, rd_data);
+        driver.write('h000, 'h0);
+        driver.read('h000, rd_data);
+
+        driver.read('h100, rd_data);
+        driver.write('h100, 'h0);
+        driver.read('h100, rd_data);
+
+        driver.read('h000, rd_data);
+        driver.write('h000, 'hFFFF_FFFF);
+        driver.read('h000, rd_data);
+
+        repeat(5) @(posedge clk);
+        $finish();
+    end
+
+endmodule

test/test_regblock.rdl

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+
+addrmap test_regblock {
+    reg my_reg {
+        field { sw=rw; hw=r; anded;} a[8] = 0x10;
+        field { sw=rw; hw=r; ored;} b[8] = 0x20;
+        field { sw=rw; hw=r; swmod;} c[8] = 0x30;
+    };
+
+    my_reg r0 @0x000;
+    my_reg r1 @0x100;
+    my_reg r2 @0x200;
+};

test/test_regblock.sv

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+// TODO: Add a banner
+module test_regblock (
+        input wire clk,
+        input wire rst,
+
+        apb3_intf.slave s_apb,
+
+        output test_regblock_pkg::test_regblock__out_t hwif_out
+    );
+
+    localparam ADDR_WIDTH = 32;
+    localparam DATA_WIDTH = 32;
+
+    //--------------------------------------------------------------------------
+    // CPU Bus interface logic
+    //--------------------------------------------------------------------------
+    logic cpuif_req;
+    logic cpuif_req_is_wr;
+    logic [ADDR_WIDTH-1:0] cpuif_addr;
+    logic [DATA_WIDTH-1:0] cpuif_wr_data;
+    logic [DATA_WIDTH-1:0] cpuif_wr_bitstrb;
+
+    logic cpuif_rd_ack;
+    logic [DATA_WIDTH-1:0] cpuif_rd_data;
+    logic cpuif_rd_err;
+
+    logic cpuif_wr_ack;
+    logic cpuif_wr_err;
+
+    begin
+        // Request
+        logic is_active;
+        always_ff @(posedge clk) begin
+            if(rst) begin
+                is_active <= '0;
+                cpuif_req <= '0;
+                cpuif_req_is_wr <= '0;
+                cpuif_addr <= '0;
+                cpuif_wr_data <= '0;
+            end else begin
+                if(~is_active) begin
+                    if(s_apb.PSEL) begin
+                        is_active <= '1;
+                        cpuif_req <= '1;
+                        cpuif_req_is_wr <= s_apb.PWRITE;
+                        cpuif_addr <= s_apb.PADDR[ADDR_WIDTH-1:0];
+                        cpuif_wr_data <= s_apb.PWDATA;
+                    end
+                end else begin
+                    cpuif_req <= '0;
+                    if(cpuif_rd_ack || cpuif_wr_ack) begin
+                        is_active <= '0;
+                    end
+                end
+            end
+        end
+        assign cpuif_wr_bitstrb = '0;
+
+        // Response
+        assign s_apb.PREADY = cpuif_rd_ack | cpuif_wr_ack;
+        assign s_apb.PRDATA = cpuif_rd_data;
+        assign s_apb.PSLVERR = cpuif_rd_err | cpuif_wr_err;
+    end
+
+    //--------------------------------------------------------------------------
+    // Address Decode
+    //--------------------------------------------------------------------------
+    typedef struct {
+        logic r0;
+        logic r1;
+        logic r2;
+    } decoded_reg_strb_t;
+    decoded_reg_strb_t decoded_reg_strb;
+    logic decoded_req;
+    logic decoded_req_is_wr;
+    logic [DATA_WIDTH-1:0] decoded_wr_data;
+    logic [DATA_WIDTH-1:0] decoded_wr_bitstrb;
+
+    always_comb begin
+        decoded_reg_strb.r0 = cpuif_req & (cpuif_addr == 'h0);
+        decoded_reg_strb.r1 = cpuif_req & (cpuif_addr == 'h100);
+        decoded_reg_strb.r2 = cpuif_req & (cpuif_addr == 'h200);
+    end
+
+    // Writes are always granted with no error response
+    assign cpuif_wr_ack = cpuif_req & cpuif_req_is_wr;
+    assign cpuif_wr_err = '0;
+
+    // Pass down signals to next stage
+    assign decoded_req = cpuif_req;
+    assign decoded_req_is_wr = cpuif_req_is_wr;
+    assign decoded_wr_data = cpuif_wr_data;
+    assign decoded_wr_bitstrb = cpuif_wr_bitstrb;
+
+    //--------------------------------------------------------------------------
+    // Field logic
+    //--------------------------------------------------------------------------
+    typedef struct {
+        struct {
+            struct {
+                logic [7:0] next;
+                logic load_next;
+            } a;
+            struct {
+                logic [7:0] next;
+                logic load_next;
+            } b;
+            struct {
+                logic [7:0] next;
+                logic load_next;
+            } c;
+        } r0;
+        struct {
+            struct {
+                logic [7:0] next;
+                logic load_next;
+            } a;
+            struct {
+                logic [7:0] next;
+                logic load_next;
+            } b;
+            struct {
+                logic [7:0] next;
+                logic load_next;
+            } c;
+        } r1;
+        struct {
+            struct {
+                logic [7:0] next;
+                logic load_next;
+            } a;
+            struct {
+                logic [7:0] next;
+                logic load_next;
+            } b;
+            struct {
+                logic [7:0] next;
+                logic load_next;
+            } c;
+        } r2;
+    } field_combo_t;
+    field_combo_t field_combo;
+
+    typedef struct {
+        struct {
+            logic [7:0] a;
+            logic [7:0] b;
+            logic [7:0] c;
+        } r0;
+        struct {
+            logic [7:0] a;
+            logic [7:0] b;
+            logic [7:0] c;
+        } r1;
+        struct {
+            logic [7:0] a;
+            logic [7:0] b;
+            logic [7:0] c;
+        } r2;
+    } field_storage_t;
+    field_storage_t field_storage;
+
+    // Field: test_regblock.r0.a
+    always_comb begin
+        field_combo.r0.a.next = field_storage.r0.a;
+        field_combo.r0.a.load_next = '0;
+        if(decoded_reg_strb.r0 && decoded_req_is_wr) begin // SW write
+            field_combo.r0.a.next = decoded_wr_data[7:0];
+            field_combo.r0.a.load_next = '1;
+        end
+    end
+    always_ff @(posedge clk) begin
+        if(rst) begin
+            field_storage.r0.a <= 'h10;
+        end else if(field_combo.r0.a.load_next) begin
+            field_storage.r0.a <= field_combo.r0.a.next;
+        end
+    end
+    assign hwif_out.r0.a.value = field_storage.r0.a;
+    assign hwif_out.r0.a.anded = &(field_storage.r0.a);
+    // Field: test_regblock.r0.b
+    always_comb begin
+        field_combo.r0.b.next = field_storage.r0.b;
+        field_combo.r0.b.load_next = '0;
+        if(decoded_reg_strb.r0 && decoded_req_is_wr) begin // SW write
+            field_combo.r0.b.next = decoded_wr_data[15:8];
+            field_combo.r0.b.load_next = '1;
+        end
+    end
+    always_ff @(posedge clk) begin
+        if(rst) begin
+            field_storage.r0.b <= 'h20;
+        end else if(field_combo.r0.b.load_next) begin
+            field_storage.r0.b <= field_combo.r0.b.next;
+        end
+    end
+    assign hwif_out.r0.b.value = field_storage.r0.b;
+    assign hwif_out.r0.b.ored = |(field_storage.r0.b);
+    // Field: test_regblock.r0.c
+    always_comb begin
+        field_combo.r0.c.next = field_storage.r0.c;
+        field_combo.r0.c.load_next = '0;
+        if(decoded_reg_strb.r0 && decoded_req_is_wr) begin // SW write
+            field_combo.r0.c.next = decoded_wr_data[23:16];
+            field_combo.r0.c.load_next = '1;
+        end
+    end
+    always_ff @(posedge clk) begin
+        if(rst) begin
+            field_storage.r0.c <= 'h30;
+        end else if(field_combo.r0.c.load_next) begin
+            field_storage.r0.c <= field_combo.r0.c.next;
+        end
+    end
+    assign hwif_out.r0.c.value = field_storage.r0.c;
+    assign hwif_out.r0.c.swmod = decoded_reg_strb.r0 && decoded_req_is_wr;
+    // Field: test_regblock.r1.a
+    always_comb begin
+        field_combo.r1.a.next = field_storage.r1.a;
+        field_combo.r1.a.load_next = '0;
+        if(decoded_reg_strb.r1 && decoded_req_is_wr) begin // SW write
+            field_combo.r1.a.next = decoded_wr_data[7:0];
+            field_combo.r1.a.load_next = '1;
+        end
+    end
+    always_ff @(posedge clk) begin
+        if(rst) begin
+            field_storage.r1.a <= 'h10;
+        end else if(field_combo.r1.a.load_next) begin
+            field_storage.r1.a <= field_combo.r1.a.next;
+        end
+    end
+    assign hwif_out.r1.a.value = field_storage.r1.a;
+    assign hwif_out.r1.a.anded = &(field_storage.r1.a);
+    // Field: test_regblock.r1.b
+    always_comb begin
+        field_combo.r1.b.next = field_storage.r1.b;
+        field_combo.r1.b.load_next = '0;
+        if(decoded_reg_strb.r1 && decoded_req_is_wr) begin // SW write
+            field_combo.r1.b.next = decoded_wr_data[15:8];
+            field_combo.r1.b.load_next = '1;
+        end
+    end
+    always_ff @(posedge clk) begin
+        if(rst) begin
+            field_storage.r1.b <= 'h20;
+        end else if(field_combo.r1.b.load_next) begin
+            field_storage.r1.b <= field_combo.r1.b.next;
+        end
+    end
+    assign hwif_out.r1.b.value = field_storage.r1.b;
+    assign hwif_out.r1.b.ored = |(field_storage.r1.b);
+    // Field: test_regblock.r1.c
+    always_comb begin
+        field_combo.r1.c.next = field_storage.r1.c;
+        field_combo.r1.c.load_next = '0;
+        if(decoded_reg_strb.r1 && decoded_req_is_wr) begin // SW write
+            field_combo.r1.c.next = decoded_wr_data[23:16];
+            field_combo.r1.c.load_next = '1;
+        end
+    end
+    always_ff @(posedge clk) begin
+        if(rst) begin
+            field_storage.r1.c <= 'h30;
+        end else if(field_combo.r1.c.load_next) begin
+            field_storage.r1.c <= field_combo.r1.c.next;
+        end
+    end
+    assign hwif_out.r1.c.value = field_storage.r1.c;
+    assign hwif_out.r1.c.swmod = decoded_reg_strb.r1 && decoded_req_is_wr;
+    // Field: test_regblock.r2.a
+    always_comb begin
+        field_combo.r2.a.next = field_storage.r2.a;
+        field_combo.r2.a.load_next = '0;
+        if(decoded_reg_strb.r2 && decoded_req_is_wr) begin // SW write
+            field_combo.r2.a.next = decoded_wr_data[7:0];
+            field_combo.r2.a.load_next = '1;
+        end
+    end
+    always_ff @(posedge clk) begin
+        if(rst) begin
+            field_storage.r2.a <= 'h10;
+        end else if(field_combo.r2.a.load_next) begin
+            field_storage.r2.a <= field_combo.r2.a.next;
+        end
+    end
+    assign hwif_out.r2.a.value = field_storage.r2.a;
+    assign hwif_out.r2.a.anded = &(field_storage.r2.a);
+    // Field: test_regblock.r2.b
+    always_comb begin
+        field_combo.r2.b.next = field_storage.r2.b;
+        field_combo.r2.b.load_next = '0;
+        if(decoded_reg_strb.r2 && decoded_req_is_wr) begin // SW write
+            field_combo.r2.b.next = decoded_wr_data[15:8];
+            field_combo.r2.b.load_next = '1;
+        end
+    end
+    always_ff @(posedge clk) begin
+        if(rst) begin
+            field_storage.r2.b <= 'h20;
+        end else if(field_combo.r2.b.load_next) begin
+            field_storage.r2.b <= field_combo.r2.b.next;
+        end
+    end
+    assign hwif_out.r2.b.value = field_storage.r2.b;
+    assign hwif_out.r2.b.ored = |(field_storage.r2.b);
+    // Field: test_regblock.r2.c
+    always_comb begin
+        field_combo.r2.c.next = field_storage.r2.c;
+        field_combo.r2.c.load_next = '0;
+        if(decoded_reg_strb.r2 && decoded_req_is_wr) begin // SW write
+            field_combo.r2.c.next = decoded_wr_data[23:16];
+            field_combo.r2.c.load_next = '1;
+        end
+    end
+    always_ff @(posedge clk) begin
+        if(rst) begin
+            field_storage.r2.c <= 'h30;
+        end else if(field_combo.r2.c.load_next) begin
+            field_storage.r2.c <= field_combo.r2.c.next;
+        end
+    end
+    assign hwif_out.r2.c.value = field_storage.r2.c;
+    assign hwif_out.r2.c.swmod = decoded_reg_strb.r2 && decoded_req_is_wr;
+
+    //--------------------------------------------------------------------------
+    // Readback
+    //--------------------------------------------------------------------------
+    
+    logic readback_err;
+    logic readback_done;
+    logic [DATA_WIDTH-1:0] readback_data;
+    logic [DATA_WIDTH-1:0] readback_array[3];
+
+    assign readback_array[0][7:0] = (decoded_reg_strb.r0 && !decoded_req_is_wr) ? field_storage.r0.a : '0;
+    assign readback_array[0][15:8] = (decoded_reg_strb.r0 && !decoded_req_is_wr) ? field_storage.r0.b : '0;
+    assign readback_array[0][23:16] = (decoded_reg_strb.r0 && !decoded_req_is_wr) ? field_storage.r0.c : '0;
+    assign readback_array[0][31:24] = '0;
+    assign readback_array[1][7:0] = (decoded_reg_strb.r1 && !decoded_req_is_wr) ? field_storage.r1.a : '0;
+    assign readback_array[1][15:8] = (decoded_reg_strb.r1 && !decoded_req_is_wr) ? field_storage.r1.b : '0;
+    assign readback_array[1][23:16] = (decoded_reg_strb.r1 && !decoded_req_is_wr) ? field_storage.r1.c : '0;
+    assign readback_array[1][31:24] = '0;
+    assign readback_array[2][7:0] = (decoded_reg_strb.r2 && !decoded_req_is_wr) ? field_storage.r2.a : '0;
+    assign readback_array[2][15:8] = (decoded_reg_strb.r2 && !decoded_req_is_wr) ? field_storage.r2.b : '0;
+    assign readback_array[2][23:16] = (decoded_reg_strb.r2 && !decoded_req_is_wr) ? field_storage.r2.c : '0;
+    assign readback_array[2][31:24] = '0;
+
+    always_comb begin
+        automatic logic [DATA_WIDTH-1:0] readback_data_var;
+        readback_done = decoded_req & ~decoded_req_is_wr;
+        readback_err = '0;
+
+        readback_data_var = '0;
+        for(int i=0; i<3; i++) begin
+            readback_data_var |= readback_array[i];
+        end
+        readback_data = readback_data_var;
+    end
+
+    always_ff @(posedge clk) begin
+        if(rst) begin
+            cpuif_rd_ack <= '0;
+            cpuif_rd_data <= '0;
+            cpuif_rd_err <= '0;
+        end else begin
+            cpuif_rd_ack <= readback_done;
+            cpuif_rd_data <= readback_data;
+            cpuif_rd_err <= readback_err;
+        end
+    end
+
+endmodule

test/test_regblock_pkg.sv

@@ -0,0 +1,85 @@
+// TODO: Add a banner
+package test_regblock_pkg;
+    
+    // test_regblock.r0.a
+    typedef struct {
+        logic [7:0] value;
+        logic anded;
+    } test_regblock__r0__a__out_t;
+
+    // test_regblock.r0.b
+    typedef struct {
+        logic [7:0] value;
+        logic ored;
+    } test_regblock__r0__b__out_t;
+
+    // test_regblock.r0.c
+    typedef struct {
+        logic [7:0] value;
+        logic swmod;
+    } test_regblock__r0__c__out_t;
+
+    // test_regblock.r0
+    typedef struct {
+        test_regblock__r0__a__out_t a;
+        test_regblock__r0__b__out_t b;
+        test_regblock__r0__c__out_t c;
+    } test_regblock__r0__out_t;
+
+    // test_regblock.r1.a
+    typedef struct {
+        logic [7:0] value;
+        logic anded;
+    } test_regblock__r1__a__out_t;
+
+    // test_regblock.r1.b
+    typedef struct {
+        logic [7:0] value;
+        logic ored;
+    } test_regblock__r1__b__out_t;
+
+    // test_regblock.r1.c
+    typedef struct {
+        logic [7:0] value;
+        logic swmod;
+    } test_regblock__r1__c__out_t;
+
+    // test_regblock.r1
+    typedef struct {
+        test_regblock__r1__a__out_t a;
+        test_regblock__r1__b__out_t b;
+        test_regblock__r1__c__out_t c;
+    } test_regblock__r1__out_t;
+
+    // test_regblock.r2.a
+    typedef struct {
+        logic [7:0] value;
+        logic anded;
+    } test_regblock__r2__a__out_t;
+
+    // test_regblock.r2.b
+    typedef struct {
+        logic [7:0] value;
+        logic ored;
+    } test_regblock__r2__b__out_t;
+
+    // test_regblock.r2.c
+    typedef struct {
+        logic [7:0] value;
+        logic swmod;
+    } test_regblock__r2__c__out_t;
+
+    // test_regblock.r2
+    typedef struct {
+        test_regblock__r2__a__out_t a;
+        test_regblock__r2__b__out_t b;
+        test_regblock__r2__c__out_t c;
+    } test_regblock__r2__out_t;
+
+    // test_regblock
+    typedef struct {
+        test_regblock__r0__out_t r0;
+        test_regblock__r1__out_t r1;
+        test_regblock__r2__out_t r2;
+    } test_regblock__out_t;
+endpackage

test/wave.do

@@ -0,0 +1,45 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /tb/rst
+add wave -noupdate /tb/clk
+add wave -noupdate /tb/apb/PSEL
+add wave -noupdate /tb/apb/PENABLE
+add wave -noupdate /tb/apb/PWRITE
+add wave -noupdate /tb/apb/PADDR
+add wave -noupdate /tb/apb/PWDATA
+add wave -noupdate /tb/apb/PRDATA
+add wave -noupdate /tb/apb/PREADY
+add wave -noupdate /tb/apb/PSLVERR
+add wave -noupdate -divider DUT
+add wave -noupdate /tb/dut/cpuif_req
+add wave -noupdate /tb/dut/cpuif_req_is_wr
+add wave -noupdate /tb/dut/cpuif_addr
+add wave -noupdate /tb/dut/cpuif_wr_data
+add wave -noupdate /tb/dut/cpuif_wr_bitstrb
+add wave -noupdate /tb/dut/cpuif_rd_ack
+add wave -noupdate /tb/dut/cpuif_rd_data
+add wave -noupdate /tb/dut/cpuif_rd_err
+add wave -noupdate /tb/dut/cpuif_wr_ack
+add wave -noupdate /tb/dut/cpuif_wr_err
+add wave -noupdate -divider Storage
+add wave -noupdate -radix hexadecimal -childformat {{/tb/dut/field_storage.r0 -radix hexadecimal -childformat {{/tb/dut/field_storage.r0.a -radix hexadecimal} {/tb/dut/field_storage.r0.b -radix hexadecimal} {/tb/dut/field_storage.r0.c -radix hexadecimal}}} {/tb/dut/field_storage.r1 -radix hexadecimal -childformat {{/tb/dut/field_storage.r1.a -radix hexadecimal} {/tb/dut/field_storage.r1.b -radix hexadecimal} {/tb/dut/field_storage.r1.c -radix hexadecimal}}} {/tb/dut/field_storage.r2 -radix hexadecimal -childformat {{/tb/dut/field_storage.r2.a -radix hexadecimal} {/tb/dut/field_storage.r2.b -radix hexadecimal} {/tb/dut/field_storage.r2.c -radix hexadecimal}}}} -expand -subitemconfig {/tb/dut/field_storage.r0 {-height 17 -radix hexadecimal -childformat {{/tb/dut/field_storage.r0.a -radix hexadecimal} {/tb/dut/field_storage.r0.b -radix hexadecimal} {/tb/dut/field_storage.r0.c -radix hexadecimal}} -expand} /tb/dut/field_storage.r0.a {-height 17 -radix hexadecimal} /tb/dut/field_storage.r0.b {-height 17 -radix hexadecimal} /tb/dut/field_storage.r0.c {-height 17 -radix hexadecimal} /tb/dut/field_storage.r1 {-height 17 -radix hexadecimal -childformat {{/tb/dut/field_storage.r1.a -radix hexadecimal} {/tb/dut/field_storage.r1.b -radix hexadecimal} {/tb/dut/field_storage.r1.c -radix hexadecimal}} -expand} /tb/dut/field_storage.r1.a {-height 17 -radix hexadecimal} /tb/dut/field_storage.r1.b {-height 17 -radix hexadecimal} /tb/dut/field_storage.r1.c {-height 17 -radix hexadecimal} /tb/dut/field_storage.r2 {-height 17 -radix hexadecimal -childformat {{/tb/dut/field_storage.r2.a -radix hexadecimal} {/tb/dut/field_storage.r2.b -radix hexadecimal} {/tb/dut/field_storage.r2.c -radix hexadecimal}} -expand} /tb/dut/field_storage.r2.a {-height 17 -radix hexadecimal} /tb/dut/field_storage.r2.b {-height 17 -radix hexadecimal} /tb/dut/field_storage.r2.c {-height 17 -radix hexadecimal}} /tb/dut/field_storage
+add wave -noupdate -divider HWIF
+add wave -noupdate -radix hexadecimal -childformat {{/tb/dut/hwif_out.r0 -radix hexadecimal -childformat {{/tb/dut/hwif_out.r0.a -radix hexadecimal -childformat {{/tb/dut/hwif_out.r0.a.value -radix hexadecimal} {/tb/dut/hwif_out.r0.a.anded -radix hexadecimal}}} {/tb/dut/hwif_out.r0.b -radix hexadecimal -childformat {{/tb/dut/hwif_out.r0.b.value -radix hexadecimal} {/tb/dut/hwif_out.r0.b.ored -radix hexadecimal}}} {/tb/dut/hwif_out.r0.c -radix hexadecimal -childformat {{/tb/dut/hwif_out.r0.c.value -radix hexadecimal} {/tb/dut/hwif_out.r0.c.swmod -radix hexadecimal}}}}} {/tb/dut/hwif_out.r1 -radix hexadecimal -childformat {{/tb/dut/hwif_out.r1.a -radix hexadecimal} {/tb/dut/hwif_out.r1.b -radix hexadecimal} {/tb/dut/hwif_out.r1.c -radix hexadecimal}}} {/tb/dut/hwif_out.r2 -radix hexadecimal -childformat {{/tb/dut/hwif_out.r2.a -radix hexadecimal} {/tb/dut/hwif_out.r2.b -radix hexadecimal} {/tb/dut/hwif_out.r2.c -radix hexadecimal}}}} -expand -subitemconfig {/tb/dut/hwif_out.r0 {-height 17 -radix hexadecimal -childformat {{/tb/dut/hwif_out.r0.a -radix hexadecimal -childformat {{/tb/dut/hwif_out.r0.a.value -radix hexadecimal} {/tb/dut/hwif_out.r0.a.anded -radix hexadecimal}}} {/tb/dut/hwif_out.r0.b -radix hexadecimal -childformat {{/tb/dut/hwif_out.r0.b.value -radix hexadecimal} {/tb/dut/hwif_out.r0.b.ored -radix hexadecimal}}} {/tb/dut/hwif_out.r0.c -radix hexadecimal -childformat {{/tb/dut/hwif_out.r0.c.value -radix hexadecimal} {/tb/dut/hwif_out.r0.c.swmod -radix hexadecimal}}}} -expand} /tb/dut/hwif_out.r0.a {-height 17 -radix hexadecimal -childformat {{/tb/dut/hwif_out.r0.a.value -radix hexadecimal} {/tb/dut/hwif_out.r0.a.anded -radix hexadecimal}} -expand} /tb/dut/hwif_out.r0.a.value {-height 17 -radix hexadecimal} /tb/dut/hwif_out.r0.a.anded {-height 17 -radix hexadecimal} /tb/dut/hwif_out.r0.b {-height 17 -radix hexadecimal -childformat {{/tb/dut/hwif_out.r0.b.value -radix hexadecimal} {/tb/dut/hwif_out.r0.b.ored -radix hexadecimal}} -expand} /tb/dut/hwif_out.r0.b.value {-height 17 -radix hexadecimal} /tb/dut/hwif_out.r0.b.ored {-height 17 -radix hexadecimal} /tb/dut/hwif_out.r0.c {-height 17 -radix hexadecimal -childformat {{/tb/dut/hwif_out.r0.c.value -radix hexadecimal} {/tb/dut/hwif_out.r0.c.swmod -radix hexadecimal}} -expand} /tb/dut/hwif_out.r0.c.value {-height 17 -radix hexadecimal} /tb/dut/hwif_out.r0.c.swmod {-height 17 -radix hexadecimal} /tb/dut/hwif_out.r1 {-height 17 -radix hexadecimal -childformat {{/tb/dut/hwif_out.r1.a -radix hexadecimal} {/tb/dut/hwif_out.r1.b -radix hexadecimal} {/tb/dut/hwif_out.r1.c -radix hexadecimal}} -expand} /tb/dut/hwif_out.r1.a {-height 17 -radix hexadecimal} /tb/dut/hwif_out.r1.b {-height 17 -radix hexadecimal} /tb/dut/hwif_out.r1.c {-height 17 -radix hexadecimal} /tb/dut/hwif_out.r2 {-height 17 -radix hexadecimal -childformat {{/tb/dut/hwif_out.r2.a -radix hexadecimal} {/tb/dut/hwif_out.r2.b -radix hexadecimal} {/tb/dut/hwif_out.r2.c -radix hexadecimal}} -expand} /tb/dut/hwif_out.r2.a {-height 17 -radix hexadecimal} /tb/dut/hwif_out.r2.b {-height 17 -radix hexadecimal} /tb/dut/hwif_out.r2.c {-height 17 -radix hexadecimal}} /tb/dut/hwif_out
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {650000 ps} 0}
+quietly wave cursor active 1
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 0
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ps
+update
+WaveRestoreZoom {252900 ps} {755184 ps}