Add Addressmap block size to generated package (#134)

* add map size as a localparam in rdl map package

* rename from _SIZE -> _BYTES_SIZE

* fix names on new test & localparam

* wrap map size in SVInt

src/peakrdl_regblock/exporter.py

@@ -20,6 +20,7 @@ from .write_buffering import WriteBuffering
 from .read_buffering import ReadBuffering
 from .external_acks import ExternalWriteAckGenerator, ExternalReadAckGenerator
 from .parity import ParityErrorReduceGenerator
+from .sv_int import SVInt
 
 if TYPE_CHECKING:
     from systemrdl.node import SignalNode
@@ -179,6 +180,7 @@ class RegblockExporter:
             "get_always_ff_event": self.dereferencer.get_always_ff_event,
             "ds": self.ds,
             "kwf": kwf,
+            "SVInt" : SVInt,
         }
 
         # Write out design

src/peakrdl_regblock/package_tmpl.sv

@@ -5,6 +5,7 @@ package {{ds.package_name}};
 
     localparam {{ds.module_name.upper()}}_DATA_WIDTH = {{ds.cpuif_data_width}};
     localparam {{ds.module_name.upper()}}_MIN_ADDR_WIDTH = {{ds.addr_width}};
+    localparam {{ds.module_name.upper()}}_SIZE = {{SVInt(ds.top_node.size)}};
 
     {{hwif.get_package_contents()|indent}}
 endpackage

tests/test_map_size/regblock.rdl

@@ -0,0 +1,5 @@
+addrmap top {
+    reg {
+        field {} f1[32] = 0;
+    } my_reg;
+};

tests/test_map_size/tb_template.sv

@@ -0,0 +1,12 @@
+{% extends "lib/tb_base.sv" %}
+
+{% block seq %}
+    {% sv_line_anchor %}
+    ##1;
+    cb.rst <= '0;
+    ##1;
+
+    // check block size
+    assert(regblock_pkg::REGBLOCK_SIZE == {{exporter.ds.top_node.size}});
+
+{% endblock %}

tests/test_map_size/testcase.py

@@ -0,0 +1,5 @@
+from ..lib.sim_testcase import SimTestCase
+
+class Test(SimTestCase):
+    def test_dut(self):
+        self.run_test()