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Aylon Chaim Porat 28ed82129f Add Addressmap block size to generated package (#134 )

* add map size as a localparam in rdl map package

* rename from _SIZE -> _BYTES_SIZE

* fix names on new test & localparam

* wrap map size in SVInt

2025-03-03 21:16:25 -08:00

2024-12-18 22:21:35 -08:00

Fix doc typos

2024-12-18 20:29:17 -08:00

2023-05-14 17:00:55 -07:00

2025-03-03 21:16:25 -08:00

2025-03-03 21:16:25 -08:00

.gitignore

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.readthedocs.yaml

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CONTRIBUTING.md

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LICENSE

initial dev

2021-06-01 21:57:12 -07:00

MANIFEST.in

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pyproject.toml

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README.md

Add coveralls

2023-03-13 21:47:33 -07:00

PeakRDL-regblock

Compile SystemRDL into a SystemVerilog control/status register (CSR) block.

For the command line tool, see the PeakRDL project.

Documentation