bslathi19/PeakRDL-regblock
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

initial dev

Browse Source
This commit is contained in:
Alex Mykyta
2021-06-01 21:51:24 -07:00
commit 292aec1c6e
3 changed files with 686 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
README.md Normal file
View File

@@ -0,0 +1,2 @@
# PeakRDL-regblock
Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.