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Fix doc typos

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This commit is contained in:
Alex Mykyta
2024-12-18 20:29:17 -08:00
parent faa57c93b9
commit 399f942201
7 changed files with 13 additions and 22 deletions
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2
docs/cpuif/introduction.rst
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@@ -11,7 +11,7 @@ Bus Width
^^^^^^^^^
The CPU interface bus width is automatically determined from the contents of the
design being exported. The bus width is equal to the widest ``accesswidth``
encountered in the deisgn.
encountered in the design.
Addressing