More testcases & documentation
This commit is contained in:
Alex Mykyta
26
doc/architecture.rst
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26
doc/architecture.rst
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Register Block Architecture
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===========================
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TODO: Add full block diagram
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CPU Interface
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-------------
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TODO: describe boundary signals. Timing diagrams
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Address Decode
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--------------
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TODO: describe boundary signals. Timing diagrams
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Field Logic
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-----------
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TODO: describe boundary signals. Timing diagrams
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Readback
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--------
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TODO: describe boundary signals. Timing diagrams
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Retiming options
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7
doc/cpuif/advanced.rst
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7
doc/cpuif/advanced.rst
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Advanced Topics
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===============
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TODO:
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* How to override an interface's name, modport, signal names, whatever
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* Creating your own custom CPU interface definition
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11
doc/cpuif/apb3.rst
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doc/cpuif/apb3.rst
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AMBA APB3
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=========
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TODO: Describe the following
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* List of interface signals
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* interface name & modports (link to advanced topics in case user wants to override)
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* flattened equivalents
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* Download link to SV interface definition
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8
doc/hwif.rst
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8
doc/hwif.rst
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Hardware Interface
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------------------
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TODO: Describe the following
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* hwif_in / hwif_out structs and their contents
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* shorthand notation used in this reference: ``hwif_in..xyz``
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* Example of how to peel back a sub-hierarchy struct
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@@ -1,6 +1,51 @@
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PeakRDL-regblock
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================
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Welcome to PeakRDL-regblock's documentation!
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============================================
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.. important::
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This project has no official releases yet and is still under active development!
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TODO: Intro text
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Installing
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----------
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Install from `PyPi`_ using pip
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.. code-block:: bash
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python3 -m pip install peakrdl-regblock
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.. _PyPi: https://pypi.org/project/peakrdl-regblock
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Links
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-----
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- `Source repository <https://github.com/SystemRDL/PeakRDL-regblock>`_
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- `Release Notes <https://github.com/SystemRDL/PeakRDL-regblock/releases>`_
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- `Issue tracker <https://github.com/SystemRDL/PeakRDL-regblock/issues>`_
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- `PyPi <https://pypi.org/project/peakrdl-regblock>`_
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- `SystemRDL Specification <http://accellera.org/downloads/standards/systemrdl>`_
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.. toctree::
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:hidden:
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self
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architecture
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hwif
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limitations
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.. toctree::
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:hidden:
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:caption: CPU Interfaces
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cpuif/apb3
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cpuif/advanced
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.. toctree::
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:hidden:
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@@ -11,4 +56,3 @@ Welcome to PeakRDL-regblock's documentation!
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props/addrmap
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props/signal
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props/rhs_props
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limitations
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@@ -2,7 +2,7 @@ Known Issues & Limitations
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==========================
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Not all SystemRDL features are supported by this exporter. For a listing of
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supported properties, see the appropriate property listing page in the previous
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supported properties, see the appropriate property listing page in the following
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sections.
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@@ -1,8 +1,8 @@
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Addrmap/Regfile Properties
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==========================
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.. note:: Any properties not explicitly listed here are either implicitly supported,
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or are not relevant to the regblock exporter and are ignored.
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.. note:: Any properties not explicitly listed here are either implicitly
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supported, or are not relevant to the regblock exporter and are ignored.
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errextbus
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@@ -14,6 +14,7 @@ sharedextbus
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|NO|
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--------------------------------------------------------------------------------
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Addrmap Properties
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==================
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@@ -1,15 +1,15 @@
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Field Properties
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================
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.. note:: Any properties not explicitly listed here are either implicitly supported,
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or are not relevant to the regblock exporter and are ignored.
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.. note:: Any properties not explicitly listed here are either implicitly
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supported, or are not relevant to the regblock exporter and are ignored.
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Software Access Properties
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--------------------------
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onread/onwrite
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^^^^^^^^^^^^^^
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|EX|
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|OK|
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rclr/rset
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^^^^^^^^^
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@@ -25,9 +25,11 @@ sw
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swacc
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^^^^^
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|EX|
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|OK|
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If true, infers an output signal ``swacc`` that is asserted as the field is sampled for a software read operation.
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If true, infers an output signal ``hwif_out..swacc`` that is asserted on the
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same clock cycle that the field is being sampled during a software read
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operation.
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.. wavedrom::
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@@ -40,9 +42,10 @@ If true, infers an output signal ``swacc`` that is asserted as the field is samp
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swmod
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^^^^^
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|EX|
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|OK|
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If true, infers an output signal ``swmod`` that is asserted as the field is being modified by software.
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If true, infers an output signal ``hwif_out..swmod`` that is asserted as the
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field is being modified by software.
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.. wavedrom::
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@@ -56,28 +59,34 @@ If true, infers an output signal ``swmod`` that is asserted as the field is bein
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swwe/swwel
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^^^^^^^^^^
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TODO: Describe result
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Provides a mechanism that allows hardware to override whether the field is
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writable by software.
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boolean
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|NO|
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|OK|
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bit
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|NO|
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If True, infers an input signal ``hwif_in..swwe`` or ``hwif_in..swwel``.
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reference
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|NO|
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|OK|
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woclr/woset
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^^^^^^^^^^^
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See ``onwrite``
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--------------------------------------------------------------------------------
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Hardware Access Properties
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--------------------------
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anded/ored/xored
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^^^^^^^^^^^^^^^^
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|EX|
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|OK|
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If true, infers the existence of output signal: ``hwif_out..anded``,
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``hwif_out..ored``, ``hwif_out..xored``
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hw
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@@ -86,19 +95,27 @@ hw
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hwclr/hwset
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^^^^^^^^^^^
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If both ``hwclr`` and ``hwset`` properties are used, and both are asserted at
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the same clock cycle, then ``hwset`` will take precedence.
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boolean
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|EX|
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|OK|
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If true, infers the existence of input signal: ``hwif_in..hwclr``, ``hwif_in..hwset``
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reference
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|EX|
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|OK|
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hwenable/hwmask
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^^^^^^^^^^^^^^^
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|EX|
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|OK|
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we/wel
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^^^^^^
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Write-enable control from hardware interface
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Write-enable control from hardware interface.
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If true, infers the existence of input signal: ``hwif_in..we``, ``hwif_in..wel``
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.. wavedrom::
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@@ -113,12 +130,14 @@ Write-enable control from hardware interface
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boolean
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|OK|
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if set, infers the existence of input signal ``hwif_in..we`` or ``hwif_in..wel``
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If true, infers the existence of input signal ``hwif_in..we`` or ``hwif_in..wel``
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reference
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|EX|
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|OK|
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--------------------------------------------------------------------------------
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Counter Properties
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------------------
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@@ -212,6 +231,8 @@ underflow
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|NO|
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--------------------------------------------------------------------------------
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Interrupt Properties
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--------------------
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@@ -244,6 +265,8 @@ stickybit
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|NO|
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--------------------------------------------------------------------------------
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Misc
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----
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@@ -1,8 +1,8 @@
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Register Properties
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===================
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.. note:: Any properties not explicitly listed here are either implicitly supported,
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or are not relevant to the regblock exporter and are ignored.
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.. note:: Any properties not explicitly listed here are either implicitly
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supported, or are not relevant to the regblock exporter and are ignored.
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accesswidth
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-----------
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@@ -1,6 +1,20 @@
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RHS Property References
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=======================
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SystemRDL allows some properties to be referenced in the righthand-side of
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property assignment expressions:
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.. code-block:: systemrdl
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some_property = my_reg.my_field->some_property;
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The official SystemRDL spec refers to these as "Ref targets" in Table G1, but
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unfortunately does not describe their semantics in much detail.
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The text below describes the interpretations used for this exporter.
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--------------------------------------------------------------------------------
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Field
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-----
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@@ -8,30 +22,68 @@ swacc
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^^^^^
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|EX|
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Single-cycle strobe that indicates the field is being sampled during a software
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read operation.
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swmod
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^^^^^
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|EX|
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Single-cycle strobe that indicates the field is being modified during a software
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access operation.
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swwe/swwel
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^^^^^^^^^^
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|EX|
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|OK|
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Represents the signal that controls the owning field's swwe/swwel behavior.
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anded/ored/xored
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^^^^^^^^^^^^^^^^
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|EX|
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Represents the current and/or/xor reduction of the owning field's value.
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hwclr/hwset
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^^^^^^^^^^^
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|EX|
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Represents the signal that controls the owning field's hwclr/hwset behavior.
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hwenable/hwmask
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^^^^^^^^^^^^^^^
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|EX|
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Represents the signal that controls the owning field's hwenable/hwmask behavior.
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we/wel
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^^^^^^
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|EX|
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next
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^^^^
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|EX|
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reset
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^^^^^
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|EX|
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resetsignal
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^^^^^^^^^^^
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|EX|
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--------------------------------------------------------------------------------
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Field Counter Properties
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------------------------
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Represents the signal that controls the owning field's we/wel behavior.
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decr
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^^^^
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|NO|
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@@ -72,6 +124,11 @@ underflow
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^^^^^^^^^
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|NO|
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--------------------------------------------------------------------------------
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Field Interrupt Properties
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--------------------------
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enable
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^^^^^^
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|EX|
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@@ -88,19 +145,8 @@ mask
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^^^^
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|EX|
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next
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^^^^
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|EX|
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reset
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^^^^^
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|EX|
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resetsignal
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^^^^^^^^^^^
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|EX|
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--------------------------------------------------------------------------------
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Register
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--------
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@@ -1,8 +1,8 @@
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Signal Properties
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=================
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.. note:: Any properties not explicitly listed here are either implicitly supported,
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or are not relevant to the regblock exporter and are ignored.
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.. note:: Any properties not explicitly listed here are either implicitly
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supported, or are not relevant to the regblock exporter and are ignored.
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activehigh/activelow
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