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This commit is contained in:
Alex Mykyta
2021-12-04 17:24:19 -08:00
parent f70bdf774c
commit 3adf7e1328
44 changed files with 827 additions and 63 deletions
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5
doc/props/addrmap.rst
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@@ -1,8 +1,8 @@
Addrmap/Regfile Properties
==========================
.. note:: Any properties not explicitly listed here are either implicitly supported,
or are not relevant to the regblock exporter and are ignored.
.. note:: Any properties not explicitly listed here are either implicitly
supported, or are not relevant to the regblock exporter and are ignored.
errextbus
@@ -14,6 +14,7 @@ sharedextbus
|NO|
--------------------------------------------------------------------------------
Addrmap Properties
==================

61
doc/props/field.rst
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@@ -1,15 +1,15 @@
Field Properties
================
.. note:: Any properties not explicitly listed here are either implicitly supported,
or are not relevant to the regblock exporter and are ignored.
.. note:: Any properties not explicitly listed here are either implicitly
supported, or are not relevant to the regblock exporter and are ignored.
Software Access Properties
--------------------------
onread/onwrite
^^^^^^^^^^^^^^
|EX|
|OK|
rclr/rset
^^^^^^^^^
@@ -25,9 +25,11 @@ sw
swacc
^^^^^
|EX|
|OK|
If true, infers an output signal ``swacc`` that is asserted as the field is sampled for a software read operation.
If true, infers an output signal ``hwif_out..swacc`` that is asserted on the
same clock cycle that the field is being sampled during a software read
operation.
.. wavedrom::
@@ -40,9 +42,10 @@ If true, infers an output signal ``swacc`` that is asserted as the field is samp
swmod
^^^^^
|EX|
|OK|
If true, infers an output signal ``swmod`` that is asserted as the field is being modified by software.
If true, infers an output signal ``hwif_out..swmod`` that is asserted as the
field is being modified by software.
.. wavedrom::
@@ -56,28 +59,34 @@ If true, infers an output signal ``swmod`` that is asserted as the field is bein
swwe/swwel
^^^^^^^^^^
TODO: Describe result
Provides a mechanism that allows hardware to override whether the field is
writable by software.
boolean
|NO|
|OK|
bit
|NO|
If True, infers an input signal ``hwif_in..swwe`` or ``hwif_in..swwel``.
reference
|NO|
|OK|
woclr/woset
^^^^^^^^^^^
See ``onwrite``
--------------------------------------------------------------------------------
Hardware Access Properties
--------------------------
anded/ored/xored
^^^^^^^^^^^^^^^^
|EX|
|OK|
If true, infers the existence of output signal: ``hwif_out..anded``,
``hwif_out..ored``, ``hwif_out..xored``
hw
@@ -86,19 +95,27 @@ hw
hwclr/hwset
^^^^^^^^^^^
If both ``hwclr`` and ``hwset`` properties are used, and both are asserted at
the same clock cycle, then ``hwset`` will take precedence.
boolean
|EX|
|OK|
If true, infers the existence of input signal: ``hwif_in..hwclr``, ``hwif_in..hwset``
reference
|EX|
|OK|
hwenable/hwmask
^^^^^^^^^^^^^^^
|EX|
|OK|
we/wel
^^^^^^
Write-enable control from hardware interface
Write-enable control from hardware interface.
If true, infers the existence of input signal: ``hwif_in..we``, ``hwif_in..wel``
.. wavedrom::
@@ -113,12 +130,14 @@ Write-enable control from hardware interface
boolean
|OK|
if set, infers the existence of input signal ``hwif_in..we`` or ``hwif_in..wel``
If true, infers the existence of input signal ``hwif_in..we`` or ``hwif_in..wel``
reference
|EX|
|OK|
--------------------------------------------------------------------------------
Counter Properties
------------------
@@ -212,6 +231,8 @@ underflow
|NO|
--------------------------------------------------------------------------------
Interrupt Properties
--------------------
@@ -244,6 +265,8 @@ stickybit
|NO|
--------------------------------------------------------------------------------
Misc
----

4
doc/props/reg.rst
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@@ -1,8 +1,8 @@
Register Properties
===================
.. note:: Any properties not explicitly listed here are either implicitly supported,
or are not relevant to the regblock exporter and are ignored.
.. note:: Any properties not explicitly listed here are either implicitly
supported, or are not relevant to the regblock exporter and are ignored.
accesswidth
-----------

72
doc/props/rhs_props.rst
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@@ -1,6 +1,20 @@
RHS Property References
=======================
SystemRDL allows some properties to be referenced in the righthand-side of
property assignment expressions:
.. code-block:: systemrdl
some_property = my_reg.my_field->some_property;
The official SystemRDL spec refers to these as "Ref targets" in Table G1, but
unfortunately does not describe their semantics in much detail.
The text below describes the interpretations used for this exporter.
--------------------------------------------------------------------------------
Field
-----
@@ -8,30 +22,68 @@ swacc
^^^^^
|EX|
Single-cycle strobe that indicates the field is being sampled during a software
read operation.
swmod
^^^^^
|EX|
Single-cycle strobe that indicates the field is being modified during a software
access operation.
swwe/swwel
^^^^^^^^^^
|EX|
|OK|
Represents the signal that controls the owning field's swwe/swwel behavior.
anded/ored/xored
^^^^^^^^^^^^^^^^
|EX|
Represents the current and/or/xor reduction of the owning field's value.
hwclr/hwset
^^^^^^^^^^^
|EX|
Represents the signal that controls the owning field's hwclr/hwset behavior.
hwenable/hwmask
^^^^^^^^^^^^^^^
|EX|
Represents the signal that controls the owning field's hwenable/hwmask behavior.
we/wel
^^^^^^
|EX|
next
^^^^
|EX|
reset
^^^^^
|EX|
resetsignal
^^^^^^^^^^^
|EX|
--------------------------------------------------------------------------------
Field Counter Properties
------------------------
Represents the signal that controls the owning field's we/wel behavior.
decr
^^^^
|NO|
@@ -72,6 +124,11 @@ underflow
^^^^^^^^^
|NO|
--------------------------------------------------------------------------------
Field Interrupt Properties
--------------------------
enable
^^^^^^
|EX|
@@ -88,19 +145,8 @@ mask
^^^^
|EX|
next
^^^^
|EX|
reset
^^^^^
|EX|
resetsignal
^^^^^^^^^^^
|EX|
--------------------------------------------------------------------------------
Register
--------

4
doc/props/signal.rst
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@@ -1,8 +1,8 @@
Signal Properties
=================
.. note:: Any properties not explicitly listed here are either implicitly supported,
or are not relevant to the regblock exporter and are ignored.
.. note:: Any properties not explicitly listed here are either implicitly
supported, or are not relevant to the regblock exporter and are ignored.
activehigh/activelow