This commit is contained in:
Alex Mykyta
2021-12-27 18:09:28 -08:00
parent 8ed45ed632
commit 48adbe142e
3 changed files with 15 additions and 25 deletions

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@@ -1,18 +0,0 @@
Interrupts seem to be pretty well-described.
Basically...
- If a register contains one or more fields that use the intr property,
then it is implied to be an interrupt register
--> Add RegNode.has_intr and RegNode.has_halt properties?
- This register implies that there is an output irq signal that is propagated to the top, and it is the OR of all interrupt field bits
- BUT in the multilevel interrupt example, perhaps this output gets suppressed?
Suppress the output signal if Reg->intr gets referenced, since this means
the user is doing a multi-level interrupt.
This means that the register's interrupt signal is "consumed" by a second-level interrupt register
- WTF about the "halt" concept?
I assume this does NOT auto-imply an output?
Mayby only imply a default halt output if:
- an interrupt register has fields that use haltenable/haltmask
- AND the interrupt register's reg->halt has not been referenced

View File

@@ -95,13 +95,21 @@ X Signals marked as field_reset or cpuif_reset need to have activehigh/activelow
specified. (8.2.1-d states that activehigh/low does not have an implied default state if unset!)
Also applies to signals referenced by resetsignal
X incrvalue/decrvalue needs to be the same or narrower than counter itself
X field shall be hw writable if "next" is assigned.
X sticky=true + "(posedge|negedge|bothedge) intr"
Edge-sensitivty doesnt make sense for full-field stickiness
X we/wel + implied or explicit "sticky"/"stickybit"
we/wel modifier doesnt make sense here.
! hwclr/hwset/we/wel probably shouldn't be able to reference itself
y->hwclr = y;
y->we = y;
... it works, but should it be allowed? Seems like user-error
X incrvalue/decrvalue needs to be the same or narrower than counter itself
! counter field that saturates should not set overflow
counter; incrsaturate; overflow;
counter; decrsaturate; underflow;
@@ -113,7 +121,7 @@ X incrvalue/decrvalue needs to be the same or narrower than counter itself
! incrwidth/decrwidth must be between 1 and the width of the counter
X field shall be hw writable if "next" is assigned.
! Illegal to use enable/mask/haltenable/haltmask on non-intr fields
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