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@@ -1,18 +0,0 @@
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Interrupts seem to be pretty well-described.
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Basically...
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- If a register contains one or more fields that use the intr property,
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then it is implied to be an interrupt register
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--> Add RegNode.has_intr and RegNode.has_halt properties?
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- This register implies that there is an output irq signal that is propagated to the top, and it is the OR of all interrupt field bits
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- BUT in the multilevel interrupt example, perhaps this output gets suppressed?
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Suppress the output signal if Reg->intr gets referenced, since this means
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the user is doing a multi-level interrupt.
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This means that the register's interrupt signal is "consumed" by a second-level interrupt register
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- WTF about the "halt" concept?
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I assume this does NOT auto-imply an output?
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Mayby only imply a default halt output if:
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- an interrupt register has fields that use haltenable/haltmask
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- AND the interrupt register's reg->halt has not been referenced
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@@ -95,13 +95,21 @@ X Signals marked as field_reset or cpuif_reset need to have activehigh/activelow
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specified. (8.2.1-d states that activehigh/low does not have an implied default state if unset!)
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specified. (8.2.1-d states that activehigh/low does not have an implied default state if unset!)
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Also applies to signals referenced by resetsignal
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Also applies to signals referenced by resetsignal
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X incrvalue/decrvalue needs to be the same or narrower than counter itself
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X field shall be hw writable if "next" is assigned.
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X sticky=true + "(posedge|negedge|bothedge) intr"
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Edge-sensitivty doesnt make sense for full-field stickiness
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X we/wel + implied or explicit "sticky"/"stickybit"
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we/wel modifier doesnt make sense here.
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! hwclr/hwset/we/wel probably shouldn't be able to reference itself
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! hwclr/hwset/we/wel probably shouldn't be able to reference itself
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y->hwclr = y;
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y->hwclr = y;
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y->we = y;
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y->we = y;
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... it works, but should it be allowed? Seems like user-error
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... it works, but should it be allowed? Seems like user-error
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X incrvalue/decrvalue needs to be the same or narrower than counter itself
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! counter field that saturates should not set overflow
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! counter field that saturates should not set overflow
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counter; incrsaturate; overflow;
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counter; incrsaturate; overflow;
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counter; decrsaturate; underflow;
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counter; decrsaturate; underflow;
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@@ -113,7 +121,7 @@ X incrvalue/decrvalue needs to be the same or narrower than counter itself
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! incrwidth/decrwidth must be between 1 and the width of the counter
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! incrwidth/decrwidth must be between 1 and the width of the counter
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X field shall be hw writable if "next" is assigned.
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! Illegal to use enable/mask/haltenable/haltmask on non-intr fields
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================================================================================
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================================================================================
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Things that need validation by this exporter
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Things that need validation by this exporter
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@@ -186,6 +186,10 @@ field -> enable
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^^^^^^^^^^^^^^^
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^^^^^^^^^^^^^^^
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|EX|
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|EX|
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field -> mask
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^^^^^^^^^^^^^
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|EX|
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field -> haltenable
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field -> haltenable
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^^^^^^^^^^^^^^^^^^^
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^^^^^^^^^^^^^^^^^^^
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|EX|
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|EX|
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@@ -194,10 +198,6 @@ field -> haltmask
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^^^^^^^^^^^^^^^^^
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^^^^^^^^^^^^^^^^^
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|EX|
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|EX|
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field -> mask
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^^^^^^^^^^^^^
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|EX|
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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