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fix doc phrasing

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Alex Mykyta
2025-08-08 17:05:58 -07:00
parent 17ceaa7c01
commit 4c819b4bcb
1 changed files with 3 additions and 3 deletions
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6
docs/rdl_features/external.rst
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@@ -17,9 +17,9 @@ Things you should know
* By default external ``hwif_out`` signals are driven combinationally. An * By default external ``hwif_out`` signals are driven combinationally. An
optional output retiming stage can be enabled if needed. optional output retiming stage can be enabled if needed.
* Due to the uncertain access latency of external components, the regblock will * Due to the uncertain access latency of external components, the regblock will
always enforce that only one outstanding transaction to an external component only issue one outstanding transaction to an external component at a time.
at a time. This is enforced even if the CPUIF is capable of pipelined accesses This is enforced even if the CPUIF is capable of pipelined accesses such as
such as AXI4-Lite. AXI4-Lite.
External Registers External Registers