bslathi19/PeakRDL-regblock
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Improve template path handling. Add synthesis tests

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This commit is contained in:
Alex Mykyta
2022-02-23 22:53:54 -08:00
parent e7e941d27b
commit 5324b594bf
32 changed files with 274 additions and 162 deletions
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105
test/lib/regblock_testcase.py → test/lib/base_testcase.py
View File

@@ -7,19 +7,14 @@ import inspect
import pathlib
import pytest
import jinja2 as jj
from systemrdl import RDLCompiler
from .sv_line_anchor import SVLineAnchor
from peakrdl.regblock import RegblockExporter
from .cpuifs.base import CpuifTestMode
from .cpuifs.apb3 import APB3
from .simulators.questa import Questa
class RegblockTestCase(unittest.TestCase):
class BaseTestCase(unittest.TestCase):
#: Path to the testcase's RDL file.
#: Relative to the testcase's dir. If unset, the first RDL file found in the
#: testcase dir will be used
@@ -39,14 +34,11 @@ class RegblockTestCase(unittest.TestCase):
retime_read_fanin = False
retime_read_response = False
#: Abort test if it exceeds this number of clock cycles
timeout_clk_cycles = 5000
simulator_cls = Questa
#: this gets auto-loaded via the _load_request autouse fixture
request = None # type: pytest.FixtureRequest
exporter = RegblockExporter()
@pytest.fixture(autouse=True)
def _load_request(self, request):
self.request = request
@@ -57,10 +49,10 @@ class RegblockTestCase(unittest.TestCase):
return class_dir
@classmethod
def get_build_dir(cls) -> str:
def get_run_dir(cls) -> str:
this_dir = cls.get_testcase_dir()
build_dir = os.path.join(this_dir, "run.out", cls.__name__)
return build_dir
run_dir = os.path.join(this_dir, "run.out", cls.__name__)
return run_dir
@classmethod
def _write_params(cls) -> None:
@@ -68,7 +60,7 @@ class RegblockTestCase(unittest.TestCase):
Write out the class parameters to a file so that it is easier to debug
how a testcase was parameterized
"""
path = os.path.join(cls.get_build_dir(), "params.txt")
path = os.path.join(cls.get_run_dir(), "params.txt")
with open(path, 'w') as f:
for k, v in cls.__dict__.items():
@@ -78,7 +70,7 @@ class RegblockTestCase(unittest.TestCase):
@classmethod
def _export_regblock(cls) -> RegblockExporter:
def _export_regblock(cls):
"""
Call the peakrdl.regblock exporter to generate the DUT
"""
@@ -94,10 +86,9 @@ class RegblockTestCase(unittest.TestCase):
rdlc.compile_file(rdl_file)
root = rdlc.elaborate(cls.rdl_elab_target, "regblock", cls.rdl_elab_params)
exporter = RegblockExporter()
exporter.export(
cls.exporter.export(
root,
cls.get_build_dir(),
cls.get_run_dir(),
module_name="regblock",
package_name="regblock_pkg",
cpuif_cls=cls.cpuif.cpuif_cls,
@@ -105,88 +96,26 @@ class RegblockTestCase(unittest.TestCase):
retime_read_response=cls.retime_read_response,
)
return exporter
@classmethod
def _generate_tb(cls, exporter: RegblockExporter):
"""
Render the testbench template into actual tb.sv
"""
template_root_path = os.path.join(os.path.dirname(__file__), "..")
loader = jj.FileSystemLoader(
template_root_path
)
jj_env = jj.Environment(
loader=loader,
undefined=jj.StrictUndefined,
extensions=[SVLineAnchor],
)
context = {
"cls": cls,
"exporter": exporter,
}
# template path needs to be relative to the Jinja loader root
template_path = os.path.join(cls.get_testcase_dir(), "tb_template.sv")
template_path = os.path.relpath(template_path, template_root_path)
template = jj_env.get_template(template_path)
output_path = os.path.join(cls.get_build_dir(), "tb.sv")
stream = template.stream(context)
stream.dump(output_path)
@classmethod
def setUpClass(cls):
# Create fresh build dir
build_dir = cls.get_build_dir()
if os.path.exists(build_dir):
shutil.rmtree(build_dir)
pathlib.Path(build_dir).mkdir(parents=True, exist_ok=True)
run_dir = cls.get_run_dir()
if os.path.exists(run_dir):
shutil.rmtree(run_dir)
pathlib.Path(run_dir).mkdir(parents=True, exist_ok=True)
cls._write_params()
# Convert testcase RDL file --> SV
exporter = cls._export_regblock()
# Create testbench from template
cls._generate_tb(exporter)
simulator = cls.simulator_cls(testcase_cls=cls)
# cd into the build directory
cwd = os.getcwd()
os.chdir(cls.get_build_dir())
try:
simulator.compile()
finally:
# cd back
os.chdir(cwd)
cls._export_regblock()
def setUp(self) -> None:
# cd into the build directory
# cd into the run directory
self.original_cwd = os.getcwd()
os.chdir(self.get_build_dir())
os.chdir(self.get_run_dir())
def run_test(self, plusargs:List[str] = None) -> None:
simulator = self.simulator_cls(testcase_cls_inst=self)
simulator.run(plusargs)
def tearDown(self) -> None:
# cd back
os.chdir(self.original_cwd)
def assertSimLogPass(self, path: str):
self.assertTrue(os.path.isfile(path))
with open(path, encoding="utf-8") as f:
for line in f:
if line.startswith("# ** Error"):
self.fail(line)
elif line.startswith("# ** Fatal"):
self.fail(line)

4
test/lib/cpuifs/apb3/__init__.py
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@@ -4,6 +4,9 @@ from peakrdl.regblock.cpuif.apb3 import APB3_Cpuif, APB3_Cpuif_flattened
class APB3(CpuifTestMode):
cpuif_cls = APB3_Cpuif
rtl_files = [
"apb3_intf.sv",
]
tb_files = [
"apb3_intf.sv",
"apb3_intf_driver.sv",
@@ -12,3 +15,4 @@ class APB3(CpuifTestMode):
class FlatAPB3(APB3):
cpuif_cls = APB3_Cpuif_flattened
rtl_files = []

4
test/lib/cpuifs/axi4lite/__init__.py
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@@ -4,6 +4,9 @@ from peakrdl.regblock.cpuif.axi4lite import AXI4Lite_Cpuif, AXI4Lite_Cpuif_flatt
class AXI4Lite(CpuifTestMode):
cpuif_cls = AXI4Lite_Cpuif
rtl_files = [
"axi4lite_intf.sv",
]
tb_files = [
"axi4lite_intf.sv",
"axi4lite_intf_driver.sv",
@@ -12,3 +15,4 @@ class AXI4Lite(CpuifTestMode):
class FlatAXI4Lite(AXI4Lite):
cpuif_cls = AXI4Lite_Cpuif_flattened
rtl_files = []

40
test/lib/cpuifs/base.py
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@@ -10,35 +10,42 @@ from ..sv_line_anchor import SVLineAnchor
if TYPE_CHECKING:
from peakrdl.regblock import RegblockExporter
from ..regblock_testcase import RegblockTestCase
from ..sim_testcase import SimTestCase
class CpuifTestMode:
cpuif_cls = None # type: CpuifBase
# Files required by the DUT
rtl_files = [] # type: List[str]
# Files required by the sim testbench
tb_files = [] # type: List[str]
tb_template = ""
def get_tb_files(self) -> List[str]:
def _translate_paths(self, files: List[str]) -> List[str]:
class_dir = os.path.dirname(inspect.getfile(self.__class__))
cwd = os.getcwd()
tb_files = []
for file in self.tb_files:
new_files = []
for file in files:
relpath = os.path.relpath(
os.path.join(class_dir, file),
cwd
)
tb_files.append(relpath)
return tb_files
if relpath not in new_files:
new_files.append(relpath)
return new_files
def get_sim_files(self) -> List[str]:
return self._translate_paths(self.rtl_files + self.tb_files)
def get_tb_inst(self, tb_cls: 'RegblockTestCase', exporter: 'RegblockExporter') -> str:
def get_synth_files(self) -> List[str]:
return self._translate_paths(self.rtl_files)
# For consistency, make the template root path relative to the test dir
template_root_path = os.path.join(os.path.dirname(__file__), "../..")
loader = jj.FileSystemLoader(
template_root_path
)
def get_tb_inst(self, tb_cls: 'SimTestCase', exporter: 'RegblockExporter') -> str:
class_dir = os.path.dirname(inspect.getfile(self.__class__))
loader = jj.FileSystemLoader(class_dir)
jj_env = jj.Environment(
loader=loader,
undefined=jj.StrictUndefined,
@@ -52,11 +59,6 @@ class CpuifTestMode:
"type": type,
}
# template paths are relative to their class.
# transform to be relative to the root path
class_dir = os.path.dirname(inspect.getfile(self.__class__))
template_local_path = os.path.join(class_dir, self.tb_template)
template_path = os.path.relpath(template_local_path, template_root_path)
template = jj_env.get_template(template_path)
template = jj_env.get_template(self.tb_template)
return template.render(context)

1
test/lib/cpuifs/passthrough/__init__.py
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@@ -4,6 +4,7 @@ from peakrdl.regblock.cpuif.passthrough import PassthroughCpuif
class Passthrough(CpuifTestMode):
cpuif_cls = PassthroughCpuif
rtl_files = []
tb_files = [
"passthrough_driver.sv",
]

69
test/lib/sim_testcase.py Normal file
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@@ -0,0 +1,69 @@
from typing import List
import os
import jinja2 as jj
from .sv_line_anchor import SVLineAnchor
from .simulators.questa import Questa
from .base_testcase import BaseTestCase
class SimTestCase(BaseTestCase):
#: Abort test if it exceeds this number of clock cycles
timeout_clk_cycles = 5000
simulator_cls = Questa
@classmethod
def _generate_tb(cls):
"""
Render the testbench template into actual tb.sv
"""
template_root_path = os.path.join(os.path.dirname(__file__), "..")
loader = jj.FileSystemLoader(
template_root_path
)
jj_env = jj.Environment(
loader=loader,
undefined=jj.StrictUndefined,
extensions=[SVLineAnchor],
)
context = {
"cls": cls,
"exporter": cls.exporter,
}
# template path needs to be relative to the Jinja loader root
template_path = os.path.join(cls.get_testcase_dir(), "tb_template.sv")
template_path = os.path.relpath(template_path, template_root_path)
template = jj_env.get_template(template_path)
output_path = os.path.join(cls.get_run_dir(), "tb.sv")
stream = template.stream(context)
stream.dump(output_path)
@classmethod
def setUpClass(cls):
super().setUpClass()
# Create testbench from template
cls._generate_tb()
simulator = cls.simulator_cls(testcase_cls=cls)
# cd into the build directory
cwd = os.getcwd()
os.chdir(cls.get_run_dir())
try:
simulator.compile()
finally:
# cd back
os.chdir(cwd)
def run_test(self, plusargs:List[str] = None) -> None:
simulator = self.simulator_cls(testcase_cls_inst=self)
simulator.run(plusargs)

6
test/lib/simulators/__init__.py
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@@ -1,18 +1,18 @@
from typing import Type, TYPE_CHECKING, List
if TYPE_CHECKING:
from ..regblock_testcase import RegblockTestCase
from ..sim_testcase import SimTestCase
class Simulator:
def __init__(self, testcase_cls: 'Type[RegblockTestCase]' = None, testcase_cls_inst: 'RegblockTestCase' = None) -> None:
def __init__(self, testcase_cls: 'Type[SimTestCase]' = None, testcase_cls_inst: 'SimTestCase' = None) -> None:
self.testcase_cls = testcase_cls
self.testcase_cls_inst = testcase_cls_inst
@property
def tb_files(self) -> List[str]:
files = []
files.extend(self.testcase_cls.cpuif.get_tb_files())
files.extend(self.testcase_cls.cpuif.get_sim_files())
files.append("regblock_pkg.sv")
files.append("regblock.sv")
files.append("tb.sv")

36
test/lib/synth_testcase.py Normal file
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@@ -0,0 +1,36 @@
from typing import List
import subprocess
import os
import pytest
from .base_testcase import BaseTestCase
@pytest.mark.skipif(os.environ.get("SKIP_SYNTH_TESTS", False), reason="user skipped")
class SynthTestCase(BaseTestCase):
def _get_synth_files(self) -> List[str]:
files = []
files.extend(self.cpuif.get_synth_files())
files.append("regblock_pkg.sv")
files.append("regblock.sv")
return files
def run_synth(self) -> None:
script = os.path.join(
os.path.dirname(__file__),
"synthesis/vivado/run.tcl"
)
cmd = [
"vivado", "-nojournal", "-notrace",
"-mode", "batch",
"-log", "out.log",
"-source", script,
"-tclargs"
]
cmd.extend(self._get_synth_files())
subprocess.run(cmd, check=True)

8
test/lib/synthesis/vivado/constr.xdc Normal file
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@@ -0,0 +1,8 @@
create_clock -period 10.000 -name clk [get_ports clk]
set_input_delay -clock [get_clocks clk] -min -add_delay 0.000 [get_ports -filter {(DIRECTION == IN) && (NAME != clk)}]
set_input_delay -clock [get_clocks clk] -max -add_delay 0.000 [get_ports -filter {(DIRECTION == IN) && (NAME != clk)}]
set_output_delay -clock [get_clocks clk] -min -add_delay 0.000 [get_ports -filter {DIRECTION == OUT}]
set_output_delay -clock [get_clocks clk] -max -add_delay 0.000 [get_ports -filter {DIRECTION == OUT}]

34
test/lib/synthesis/vivado/run.tcl Normal file
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@@ -0,0 +1,34 @@
set this_dir [file dirname [file normalize [info script]]]
set files $argv
# Multi-driven
set_msg_config -id {[Synth 8-6858]} -new_severity "ERROR"
set_msg_config -id {[Synth 8-6859]} -new_severity "ERROR"
# Implicit net
set_msg_config -id {[Synth 8-992]} -new_severity "ERROR"
# Non-combo always_comb
set_msg_config -id {[Synth 8-87]} -new_severity "ERROR"
# Latch
set_msg_config -id {[Synth 8-327]} -new_severity "ERROR"
# Timing loop
set_msg_config -id {[Synth 8-295]} -new_severity "ERROR"
# Promote all critical warnings to errors
set_msg_config -severity {CRITICAL WARNING} -new_severity "ERROR"
set_part xczu7eg-ffvf1517-2-i
read_verilog -sv $files
read_xdc $this_dir/constr.xdc
synth_design -top regblock -mode out_of_context
#write_checkpoint -force synth.dcp
if {[get_msg_config -count -severity {CRITICAL WARNING}] || [get_msg_config -count -severity ERROR]} {
error "Encountered errors"
}