bslathi19/PeakRDL-regblock
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Remove use of in-scope initial assignments to automatics to work around bug in Spyglass lint tool. #87

Browse Source
This commit is contained in:
Alex Mykyta
2024-03-20 19:57:50 -07:00
parent cf2be63c20
commit 555efdfcc0
2 changed files with 8 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/peakrdl_regblock/field_logic/templates/field_storage.sv
View File

@@ -1,8 +1,10 @@
{%- import 'field_logic/templates/counter_macros.sv' as counter_macros with context -%}
// Field: {{node.get_path()}}
always_comb begin
automatic logic [{{node.width-1}}:0] next_c = {{field_logic.get_storage_identifier(node)}};
automatic logic load_next_c = '0;
automatic logic [{{node.width-1}}:0] next_c;
automatic logic load_next_c;
next_c = {{field_logic.get_storage_identifier(node)}};
load_next_c = '0;
{%- for signal in extra_combo_signals %}
{{field_logic.get_field_combo_identifier(node, signal.name)}} = {{signal.default_assignment}};

6
src/peakrdl_regblock/module_tmpl.sv
View File

@@ -134,7 +134,8 @@ module {{ds.module_name}} (
always_comb begin
{%- if ds.has_external_addressable %}
automatic logic is_external = '0;
automatic logic is_external;
is_external = '0;
{%- endif %}
{{address_decode.get_implementation()|indent(8)}}
{%- if ds.has_external_addressable %}
@@ -186,7 +187,8 @@ module {{ds.module_name}} (
if({{get_resetsignal(cpuif.reset)}}) begin
parity_error <= '0;
end else begin
automatic logic err = '0;
automatic logic err;
err = '0;
{{parity.get_implementation()|indent(12)}}
parity_error <= err;
end