Doc fixes. Add banner to output

2022-03-16 20:53:55 -07:00
parent b9570480be
commit 746f6cb020
7 changed files with 12 additions and 9 deletions
--- a/docs/architecture.rst
+++ b/docs/architecture.rst
@@ -3,7 +3,7 @@ Register Block Architecture

 The generated register block RTL is organized into several sections.
 Each section is automatically generated based on the source register model and
-is rendered into the output register block SystermVerilog RTL.
+is rendered into the output register block SystemVerilog RTL.

 .. figure:: diagrams/arch.png