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Doc fixes. Add banner to output

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This commit is contained in:
Alex Mykyta
2022-03-16 20:53:55 -07:00
parent b9570480be
commit 746f6cb020
7 changed files with 12 additions and 9 deletions
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4
docs/cpuif/apb3.rst
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@@ -10,10 +10,10 @@ The APB3 CPU interface comes in two i/o port flavors:
SystemVerilog Interface
Class: :class:`peakrdl.regblock.cpuif.apb3.APB3_Cpuif`
Interface Definition: :download:`apb3_intf.sv <../../test/lib/cpuifs/apb3/apb3_intf.sv>`
Interface Definition: :download:`apb3_intf.sv <../../tests/lib/cpuifs/apb3/apb3_intf.sv>`
Flattened inputs/outputs
Flattens the interface into descrete input and output ports.
Flattens the interface into discrete input and output ports.
Class: :class:`peakrdl.regblock.cpuif.apb3.APB3_Cpuif_flattened`

4
docs/cpuif/axi4lite.rst
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@@ -12,10 +12,10 @@ The AXI4-Lite CPU interface comes in two i/o port flavors:
SystemVerilog Interface
Class: :class:`peakrdl.regblock.cpuif.axi4lite.AXI4Lite_Cpuif`
Interface Definition: :download:`apb3_intf.sv <../../test/lib/cpuifs/axi4lite/axi4lite_intf.sv>`
Interface Definition: :download:`axi4lite_intf.sv <../../tests/lib/cpuifs/axi4lite/axi4lite_intf.sv>`
Flattened inputs/outputs
Flattens the interface into descrete input and output ports.
Flattens the interface into discrete input and output ports.
Class: :class:`peakrdl.regblock.cpuif.axi4lite.AXI4Lite_Cpuif_flattened`