bslathi19/PeakRDL-regblock
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Update peakrdl plugin to extend from base class

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This commit is contained in:
Alex Mykyta
2023-02-17 23:14:50 -08:00
parent 6026e3398e
commit 7fcd0e599b
1 changed files with 3 additions and 1 deletions
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4
src/peakrdl_regblock/__peakrdl__.py
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@@ -1,5 +1,7 @@
from typing import TYPE_CHECKING from typing import TYPE_CHECKING
from peakrdl.plugins.exporter import ExporterSubcommandPlugin #pylint: disable=import-error
from .exporter import RegblockExporter from .exporter import RegblockExporter
from .cpuif import apb3, apb4, axi4lite, passthrough, CpuifBase from .cpuif import apb3, apb4, axi4lite, passthrough, CpuifBase
from .udps import ALL_UDPS from .udps import ALL_UDPS
@@ -31,7 +33,7 @@ for ep, dist in entry_points.get_entry_points("peakrdl_regblock.cpuif"):
CPUIF_DICT[name] = cpuif CPUIF_DICT[name] = cpuif
class Exporter: class Exporter(ExporterSubcommandPlugin):
short_desc = "Generate a SystemVerilog control/status register (CSR) block" short_desc = "Generate a SystemVerilog control/status register (CSR) block"
udp_definitions = ALL_UDPS udp_definitions = ALL_UDPS