Re-enable xsim for testcases. Works better in Vivado 2024.2

tests/lib/simulators/xilinx.py

@@ -6,15 +6,6 @@ import shutil
 from .base import Simulator
 
 class XilinxXSIM(Simulator):
-    """
-    Avoid using the Xilinx simulator... Its buggy and extraordinarily slow.
-    As observed in v2023.2:
-        - Clocking block assignments to struct members do not simulate correctly.
-          assignment statements get lost.
-            https://support.xilinx.com/s/question/0D54U00007ZIGfXSAX/xsim-bug-xsim-does-not-simulate-struct-assignments-in-clocking-blocks-correctly?language=en_US
-        - Streaming bit-swap within a conditional returns a corrupted value
-            https://support.xilinx.com/s/question/0D54U00007ZIIBPSA5/xsim-bug-xsim-corrupts-value-of-signal-that-is-bitswapped-within-a-conditional-operator?language=en_US
-    """
     name = "xsim"
 
     @classmethod

tests/lib/synthesizers/vivado_scripts/run.tcl

@@ -22,7 +22,7 @@ set_msg_config -id {[Synth 8-295]} -new_severity "ERROR"
 set_msg_config -severity {CRITICAL WARNING} -new_severity "ERROR"
 
 
-set_part xczu7eg-ffvf1517-2-i
+set_part [lindex [get_parts] 0]
 read_verilog -sv $files
 read_xdc $this_dir/constr.xdc
 synth_design -top regblock -mode out_of_context