Increment version

docs/index.rst

@@ -10,35 +10,16 @@ your hardware design.
 * Options for many popular CPU interface protocols (AMBA APB, AXI4-Lite, and more)
 * Configurable pipelining options for designs with fast clock rates.
 * Broad support for SystemRDL 2.0 features
-* Fully synthesizable SystemVerilog. Tested on Xilinx/AMD's Vivado & Intel Quartus
-
-.. warning::
-
-    The PeakRDL-regblock SV generator is still in pre-production (v0.x version numbers).
-    During this time, I may decide to refactor things which could affect compatibility.
 
 
-Installing
-----------
-
-Install from `PyPi`_ using pip
-
-.. code-block:: bash
-
-    python3 -m pip install peakrdl-regblock
-
-.. _PyPi: https://pypi.org/project/peakrdl-regblock
-
-
-
-Example
--------
+Quick Start
+-----------
 The easiest way to use PeakRDL-regblock is via the  `PeakRDL command line tool <https://peakrdl.readthedocs.io/>`_:
 
 .. code-block:: bash
 
-    # Install the command line tool
-    python3 -m pip install peakrdl
+    # Install PeakRDL-regblock along with the command-line tool
+    python3 -m pip install peakrdl-regblock[cli]
 
     # Export!
     peakrdl regblock atxmega_spi.rdl -o regblock/ --cpuif axi4-lite

src/peakrdl_regblock/__about__.py

@@ -1,2 +1,2 @@
-version_info = (0, 23, 0)
+version_info = (1, 0, 0)
 __version__ = ".".join([str(n) for n in version_info])