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Re-enable xsim for testcases. Works better in Vivado 2024.2

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This commit is contained in:
Alex Mykyta
2025-04-11 22:19:19 -07:00
parent 06bd567750
commit 833c515cd2
16 changed files with 7 additions and 38 deletions
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6
tests/test_interrupts/tb_template.sv
View File

@@ -112,7 +112,6 @@
cpuif.assert_read('h10, 'h000);
assert(cb.hwif_out.level_irqs_we.intr == 1'b0);
cb.hwif_in.level_irqs_we.irq0.next <= 'h0F;
assert(cb.hwif_in.level_irqs_we.irq0.next == 8'h00);
@cb;
cb.hwif_in.level_irqs_we.irq0.next <= 'h00;
assert(cb.hwif_out.level_irqs_we.intr == 1'b0);
@@ -123,7 +122,6 @@
assert(cb.hwif_out.level_irqs_we.intr == 1'b0);
cb.hwif_in.level_irqs_we.irq0.next <= 'h0F;
@cb;
assert(cb.hwif_in.level_irqs_we.irq0.next == 8'h0F);
cpuif.assert_read('h10, 'h00F);
assert(cb.hwif_out.level_irqs_we.intr == 1'b1);
cpuif.write('h110, 'h0); // disable ctrl_we
@@ -138,20 +136,16 @@
cpuif.assert_read('h14, 'h000);
assert(cb.hwif_out.level_irqs_wel.intr == 1'b0);
cb.hwif_in.level_irqs_wel.irq0.next <= 'h0F;
assert(cb.hwif_in.level_irqs_wel.irq0.next == 8'h00);
@cb;
cb.hwif_in.level_irqs_wel.irq0.next <= 'h00;
cpuif.assert_read('h14, 'h000);
assert(cb.hwif_in.level_irqs_wel.irq0.next == 8'h00);
assert(cb.hwif_out.level_irqs_wel.intr == 1'b0);
cpuif.write('h114, 'h2); // enable ctrl_we
@cb;
cpuif.assert_read('h14, 'h000);
assert(cb.hwif_in.level_irqs_wel.irq0.next == 8'h00);
assert(cb.hwif_out.level_irqs_wel.intr == 1'b0);
cb.hwif_in.level_irqs_wel.irq0.next <= 'h0F;
@cb;
assert(cb.hwif_in.level_irqs_wel.irq0.next == 8'h0F);
cpuif.assert_read('h14, 'h00F);
assert(cb.hwif_out.level_irqs_wel.intr == 1'b1);
cpuif.write('h114, 'h3); // disable ctrl_we

1
tests/test_interrupts/testcase.py
View File

@@ -1,6 +1,5 @@
from ..lib.sim_testcase import SimTestCase
class Test(SimTestCase):
incompatible_sim_tools = {"xsim"} # due to cb struct assignment bug
def test_dut(self):
self.run_test()