bslathi19/PeakRDL-regblock
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Re-enable xsim for testcases. Works better in Vivado 2024.2

Browse Source
This commit is contained in:
Alex Mykyta
2025-04-11 22:19:19 -07:00
parent 06bd567750
commit 833c515cd2
16 changed files with 7 additions and 38 deletions
Download Patch File Download Diff File Expand all files Collapse all files

15
tests/test_structural_sw_rw/tb_template.sv
View File

@@ -71,13 +71,10 @@
cpuif.assert_read('h3000, 'h4DEAB000);
// rw_reg_lsb0
`ifndef XILINX_XSIM
// Skip due to xsim bug simulating internal RTL - bitswap inside conditional corrupts data
cpuif.assert_read('h3004, 0);
cpuif.write('h3004, 'h4DEAB000);
@cb;
assert(`bitswap(cb.hwif_out.rw_reg_lsb0.f1.value) == 8'hAB);
assert(`bitswap(cb.hwif_out.rw_reg_lsb0.f2.value) == 11'h4DE);
cpuif.assert_read('h3004, 'h4DEAB000);
`endif
cpuif.assert_read('h3004, 0);
cpuif.write('h3004, 'h4DEAB000);
@cb;
assert(`bitswap(cb.hwif_out.rw_reg_lsb0.f1.value) == 8'hAB);
assert(`bitswap(cb.hwif_out.rw_reg_lsb0.f2.value) == 11'h4DE);
cpuif.assert_read('h3004, 'h4DEAB000);
{% endblock %}