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This commit is contained in:
Alex Mykyta
2022-06-09 20:24:53 -07:00
parent 693040d145
commit 8d13a9d7fe
52 changed files with 26 additions and 27 deletions
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4
docs/cpuif/apb3.rst
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@@ -8,14 +8,14 @@ CPU interface.
The APB3 CPU interface comes in two i/o port flavors:
SystemVerilog Interface
Class: :class:`peakrdl.regblock.cpuif.apb3.APB3_Cpuif`
Class: :class:`peakrdl_regblock.cpuif.apb3.APB3_Cpuif`
Interface Definition: :download:`apb3_intf.sv <../../tests/lib/cpuifs/apb3/apb3_intf.sv>`
Flattened inputs/outputs
Flattens the interface into discrete input and output ports.
Class: :class:`peakrdl.regblock.cpuif.apb3.APB3_Cpuif_flattened`
Class: :class:`peakrdl_regblock.cpuif.apb3.APB3_Cpuif_flattened`
.. warning::

4
docs/cpuif/axi4lite.rst
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@@ -10,14 +10,14 @@ CPU interface.
The AXI4-Lite CPU interface comes in two i/o port flavors:
SystemVerilog Interface
Class: :class:`peakrdl.regblock.cpuif.axi4lite.AXI4Lite_Cpuif`
Class: :class:`peakrdl_regblock.cpuif.axi4lite.AXI4Lite_Cpuif`
Interface Definition: :download:`axi4lite_intf.sv <../../tests/lib/cpuifs/axi4lite/axi4lite_intf.sv>`
Flattened inputs/outputs
Flattens the interface into discrete input and output ports.
Class: :class:`peakrdl.regblock.cpuif.axi4lite.AXI4Lite_Cpuif_flattened`
Class: :class:`peakrdl_regblock.cpuif.axi4lite.AXI4Lite_Cpuif_flattened`
Pipelined Performance

4
docs/cpuif/customizing.rst
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@@ -28,7 +28,7 @@ Rather than rewriting a new CPU interface definition, you can extend and adjust
.. code-block:: python
from peakrdl.regblock.cpuif.axi4lite import AXI4Lite_Cpuif
from peakrdl_regblock.cpuif.axi4lite import AXI4Lite_Cpuif
class My_AXI4Lite(AXI4Lite_Cpuif):
@property
@@ -70,7 +70,7 @@ you can define your own.
2. Create a Python class that defines your CPUIF
Extend your class from :class:`peakrdl.regblock.cpuif.CpuifBase`.
Extend your class from :class:`peakrdl_regblock.cpuif.CpuifBase`.
Define the port declaration string, and provide a reference to your template file.
3. Use your new CPUIF definition when exporting!

2
docs/cpuif/passthrough.rst
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@@ -4,6 +4,6 @@ CPUIF Passthrough
This CPUIF mode bypasses the protocol converter stage and directly exposes the
internal CPUIF handshake signals to the user.
Class: :class:`peakrdl.regblock.cpuif.passthrough.PassthroughCpuif`
Class: :class:`peakrdl_regblock.cpuif.passthrough.PassthroughCpuif`
For more details on the protocol itself, see: :ref:`cpuif_protocol`.