8d13a9d7fe99e0a93a3a96c8877793bfee691679
PeakRDL-regblock
Compile SystemRDL into a SystemVerilog control/status register (CSR) block
Documentation
See the PeakRDL-regblock Documentation for more details
Description
Languages
Python
56.8%
SystemVerilog
42.8%
Tcl
0.3%
Shell
0.1%