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Alex Mykyta
2022-06-09 20:24:53 -07:00
parent 693040d145
commit 8d13a9d7fe
52 changed files with 26 additions and 27 deletions
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docs/cpuif/axi4lite.rst
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@@ -10,14 +10,14 @@ CPU interface.
The AXI4-Lite CPU interface comes in two i/o port flavors:
SystemVerilog Interface
Class: :class:`peakrdl.regblock.cpuif.axi4lite.AXI4Lite_Cpuif`
Class: :class:`peakrdl_regblock.cpuif.axi4lite.AXI4Lite_Cpuif`
Interface Definition: :download:`axi4lite_intf.sv <../../tests/lib/cpuifs/axi4lite/axi4lite_intf.sv>`
Flattened inputs/outputs
Flattens the interface into discrete input and output ports.
Class: :class:`peakrdl.regblock.cpuif.axi4lite.AXI4Lite_Cpuif_flattened`
Class: :class:`peakrdl_regblock.cpuif.axi4lite.AXI4Lite_Cpuif_flattened`
Pipelined Performance