Switch to use regular non-namespaced package

src/peakrdl_regblock/cpuif/__init__.py

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+from .base import CpuifBase

src/peakrdl_regblock/cpuif/apb3/__init__.py

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+from ..base import CpuifBase
+
+class APB3_Cpuif(CpuifBase):
+    template_path = "apb3_tmpl.sv"
+
+    @property
+    def port_declaration(self) -> str:
+        return "apb3_intf.slave s_apb"
+
+    def signal(self, name:str) -> str:
+        return "s_apb." + name.upper()
+
+
+class APB3_Cpuif_flattened(APB3_Cpuif):
+    @property
+    def port_declaration(self) -> str:
+        lines = [
+            "input wire " + self.signal("psel"),
+            "input wire " + self.signal("penable"),
+            "input wire " + self.signal("pwrite"),
+            f"input wire [{self.addr_width-1}:0] " + self.signal("paddr"),
+            f"input wire [{self.data_width-1}:0] " + self.signal("pwdata"),
+            "output logic " + self.signal("pready"),
+            f"output logic [{self.data_width-1}:0] " + self.signal("prdata"),
+            "output logic " + self.signal("pslverr"),
+        ]
+        return ",\n".join(lines)
+
+    def signal(self, name:str) -> str:
+        return "s_apb_" + name

src/peakrdl_regblock/cpuif/apb3/apb3_tmpl.sv

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+// Request
+logic is_active;
+always_ff {{get_always_ff_event(cpuif.reset)}} begin
+    if({{get_resetsignal(cpuif.reset)}}) begin
+        is_active <= '0;
+        cpuif_req <= '0;
+        cpuif_req_is_wr <= '0;
+        cpuif_addr <= '0;
+        cpuif_wr_data <= '0;
+    end else begin
+        if(~is_active) begin
+            if({{cpuif.signal("psel")}}) begin
+                is_active <= '1;
+                cpuif_req <= '1;
+                cpuif_req_is_wr <= {{cpuif.signal("pwrite")}};
+                {%- if cpuif.data_width == 8 %}
+                cpuif_addr <= {{cpuif.signal("paddr")}}[{{cpuif.addr_width-1}}:0];
+                {%- else %}
+                cpuif_addr <= { {{-cpuif.signal("paddr")}}[{{cpuif.addr_width-1}}:{{clog2(cpuif.data_width//8)}}], {{clog2(cpuif.data_width//8)}}'b0};
+                {%- endif %}
+                cpuif_wr_data <= {{cpuif.signal("pwdata")}};
+            end
+        end else begin
+            cpuif_req <= '0;
+            if(cpuif_rd_ack || cpuif_wr_ack) begin
+                is_active <= '0;
+            end
+        end
+    end
+end
+
+// Response
+assign {{cpuif.signal("pready")}} = cpuif_rd_ack | cpuif_wr_ack;
+assign {{cpuif.signal("prdata")}} = cpuif_rd_data;
+assign {{cpuif.signal("pslverr")}} = cpuif_rd_err | cpuif_wr_err;

src/peakrdl_regblock/cpuif/axi4lite/__init__.py

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+from ..base import CpuifBase
+
+class AXI4Lite_Cpuif(CpuifBase):
+    template_path = "axi4lite_tmpl.sv"
+
+    @property
+    def port_declaration(self) -> str:
+        return "axi4lite_intf.slave s_axil"
+
+    def signal(self, name:str) -> str:
+        return "s_axil." + name.upper()
+
+    @property
+    def data_width_bytes(self) -> int:
+        return self.data_width // 8
+
+    @property
+    def regblock_latency(self) -> int:
+        return max(self.exp.min_read_latency, self.exp.min_write_latency)
+
+    @property
+    def max_outstanding(self) -> int:
+        """
+        Best pipelined performance is when the max outstanding transactions
+        is the design's latency + 2.
+        Anything beyond that does not have any effect, aside from adding unnecessary
+        logic and additional buffer-bloat latency.
+        """
+        return self.regblock_latency + 2
+
+    @property
+    def resp_buffer_size(self) -> int:
+        """
+        Response buffer size must be greater or equal to max outstanding
+        transactions to prevent response overrun.
+        """
+        return self.max_outstanding
+
+
+class AXI4Lite_Cpuif_flattened(AXI4Lite_Cpuif):
+    @property
+    def port_declaration(self) -> str:
+        lines = [
+            "output logic " + self.signal("awready"),
+            "input wire " + self.signal("awvalid"),
+            f"input wire [{self.addr_width-1}:0] " + self.signal("awaddr"),
+            "input wire [2:0] " + self.signal("awprot"),
+
+            "output logic " + self.signal("wready"),
+            "input wire " + self.signal("wvalid"),
+            f"input wire [{self.data_width-1}:0] " + self.signal("wdata"),
+            f"input wire [{self.data_width//8-1}:0]" + self.signal("wstrb"),
+
+            "input wire " + self.signal("bready"),
+            "output logic " + self.signal("bvalid"),
+            "output logic [1:0] " + self.signal("bresp"),
+
+            "output logic " + self.signal("arready"),
+            "input wire " + self.signal("arvalid"),
+            f"input wire [{self.addr_width-1}:0] " + self.signal("araddr"),
+            "input wire [2:0] " + self.signal("arprot"),
+
+            "input wire " + self.signal("rready"),
+            "output logic " + self.signal("rvalid"),
+            f"output logic [{self.data_width-1}:0] " + self.signal("rdata"),
+            "output logic [1:0] " + self.signal("rresp"),
+        ]
+        return ",\n".join(lines)
+
+    def signal(self, name:str) -> str:
+        return "s_axil_" + name

src/peakrdl_regblock/cpuif/axi4lite/axi4lite_tmpl.sv

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+// Max Outstanding Transactions: {{cpuif.max_outstanding}}
+logic [{{clog2(cpuif.max_outstanding+1)-1}}:0] axil_n_in_flight;
+logic axil_prev_was_rd;
+logic axil_arvalid;
+logic [{{cpuif.addr_width-1}}:0] axil_araddr;
+logic axil_ar_accept;
+logic axil_awvalid;
+logic [{{cpuif.addr_width-1}}:0] axil_awaddr;
+logic axil_wvalid;
+logic [{{cpuif.data_width-1}}:0] axil_wdata;
+logic axil_aw_accept;
+logic axil_resp_acked;
+
+// Transaction request accpetance
+always_ff {{get_always_ff_event(cpuif.reset)}} begin
+    if({{get_resetsignal(cpuif.reset)}}) begin
+        axil_prev_was_rd <= '0;
+        axil_arvalid <= '0;
+        axil_araddr <= '0;
+        axil_awvalid <= '0;
+        axil_awaddr <= '0;
+        axil_wvalid <= '0;
+        axil_wdata <= '0;
+        axil_n_in_flight <= '0;
+    end else begin
+        // AR* acceptance register
+        if(axil_ar_accept) begin
+            axil_prev_was_rd <= '1;
+            axil_arvalid <= '0;
+        end
+        if({{cpuif.signal("arvalid")}} && {{cpuif.signal("arready")}}) begin
+            axil_arvalid <= '1;
+            axil_araddr <= {{cpuif.signal("araddr")}};
+        end
+
+        // AW* & W* acceptance registers
+        if(axil_aw_accept) begin
+            axil_prev_was_rd <= '0;
+            axil_awvalid <= '0;
+            axil_wvalid <= '0;
+        end
+        if({{cpuif.signal("awvalid")}} && {{cpuif.signal("awready")}}) begin
+            axil_awvalid <= '1;
+            axil_awaddr <= {{cpuif.signal("awaddr")}};
+        end
+        if({{cpuif.signal("wvalid")}} && {{cpuif.signal("wready")}}) begin
+            axil_wvalid <= '1;
+            axil_wdata <= {{cpuif.signal("wdata")}};
+        end
+
+        // Keep track of in-flight transactions
+        if((axil_ar_accept || axil_aw_accept) && !axil_resp_acked) begin
+            axil_n_in_flight <= axil_n_in_flight + 1'b1;
+        end else if(!(axil_ar_accept || axil_aw_accept) && axil_resp_acked) begin
+            axil_n_in_flight <= axil_n_in_flight - 1'b1;
+        end
+    end
+end
+
+always_comb begin
+    {{cpuif.signal("arready")}} = (!axil_arvalid || axil_ar_accept);
+    {{cpuif.signal("awready")}} = (!axil_awvalid || axil_aw_accept);
+    {{cpuif.signal("wready")}} = (!axil_wvalid || axil_aw_accept);
+end
+
+// Request dispatch
+always_comb begin
+    cpuif_wr_data = axil_wdata;
+    cpuif_req = '0;
+    cpuif_req_is_wr = '0;
+    cpuif_addr = '0;
+    axil_ar_accept = '0;
+    axil_aw_accept = '0;
+
+    if(axil_n_in_flight < 'd{{cpuif.max_outstanding}}) begin
+        // Can safely issue more transactions without overwhelming response buffer
+        if(axil_arvalid && !axil_prev_was_rd) begin
+            cpuif_req = '1;
+            cpuif_req_is_wr = '0;
+            cpuif_addr = axil_araddr;
+            if(!cpuif_req_stall_rd) axil_ar_accept = '1;
+        end else if(axil_awvalid && axil_wvalid) begin
+            cpuif_req = '1;
+            cpuif_req_is_wr = '1;
+            cpuif_addr = axil_awaddr;
+            if(!cpuif_req_stall_wr) axil_aw_accept = '1;
+        end else if(axil_arvalid) begin
+            cpuif_req = '1;
+            cpuif_req_is_wr = '0;
+            cpuif_addr = axil_araddr;
+            if(!cpuif_req_stall_rd) axil_ar_accept = '1;
+        end
+    end
+end
+
+
+// AXI4-Lite Response Logic
+{%- if cpuif.resp_buffer_size == 1 %}
+always_ff {{get_always_ff_event(cpuif.reset)}} begin
+    if({{get_resetsignal(cpuif.reset)}}) begin
+        {{cpuif.signal("rvalid")}} <= '0;
+        {{cpuif.signal("rresp")}} <= '0;
+        {{cpuif.signal("rdata")}} <= '0;
+        {{cpuif.signal("bvalid")}} <= '0;
+        {{cpuif.signal("bresp")}} <= '0;
+    end else begin
+        if({{cpuif.signal("rvalid")}} && {{cpuif.signal("rready")}}) begin
+            {{cpuif.signal("rvalid")}} <= '0;
+        end
+
+        if({{cpuif.signal("bvalid")}} && {{cpuif.signal("bready")}}) begin
+            {{cpuif.signal("bvalid")}} <= '0;
+        end
+
+        if(cpuif_rd_ack) begin
+            {{cpuif.signal("rvalid")}} <= '1;
+            {{cpuif.signal("rdata")}} <= cpuif_rd_data;
+            if(cpuif_rd_err) {{cpuif.signal("rresp")}} <= 2'b10; // SLVERR
+            else {{cpuif.signal("rresp")}} <= 2'b00; // OKAY
+        end
+
+        if(cpuif_wr_ack) begin
+            {{cpuif.signal("bvalid")}} <= '1;
+            if(cpuif_wr_err) {{cpuif.signal("bresp")}} <= 2'b10; // SLVERR
+            else {{cpuif.signal("bresp")}} <= 2'b00; // OKAY
+        end
+    end
+end
+
+always_comb begin
+    axil_resp_acked = '0;
+    if({{cpuif.signal("rvalid")}} && {{cpuif.signal("rready")}}) axil_resp_acked = '1;
+    if({{cpuif.signal("bvalid")}} && {{cpuif.signal("bready")}}) axil_resp_acked = '1;
+end
+
+{%- else %}
+struct {
+    logic is_wr;
+    logic err;
+    logic [{{cpuif.data_width-1}}:0] rdata;
+} axil_resp_buffer[{{roundup_pow2(cpuif.resp_buffer_size)}}];
+{%- if not is_pow2(cpuif.resp_buffer_size) %}
+// axil_resp_buffer is intentionally padded to the next power of two despite
+// only requiring {{cpuif.resp_buffer_size}} entries.
+// This is to avoid quirks in some tools that cannot handle indexing into a non-power-of-2 array.
+// Unused entries are expected to be optimized away
+{% endif %}
+
+logic [{{clog2(cpuif.resp_buffer_size)}}:0] axil_resp_wptr;
+logic [{{clog2(cpuif.resp_buffer_size)}}:0] axil_resp_rptr;
+
+always_ff {{get_always_ff_event(cpuif.reset)}} begin
+    if({{get_resetsignal(cpuif.reset)}}) begin
+        for(int i=0; i<{{cpuif.resp_buffer_size}}; i++) begin
+            axil_resp_buffer[i].is_wr <= '0;
+            axil_resp_buffer[i].err <= '0;
+            axil_resp_buffer[i].rdata <= '0;
+        end
+        axil_resp_wptr <= '0;
+        axil_resp_rptr <= '0;
+    end else begin
+        // Store responses in buffer until AXI response channel accepts them
+        if(cpuif_rd_ack || cpuif_wr_ack) begin
+            if(cpuif_rd_ack) begin
+                axil_resp_buffer[axil_resp_wptr[{{clog2(cpuif.resp_buffer_size)-1}}:0]].is_wr <= '0;
+                axil_resp_buffer[axil_resp_wptr[{{clog2(cpuif.resp_buffer_size)-1}}:0]].err <= cpuif_rd_err;
+                axil_resp_buffer[axil_resp_wptr[{{clog2(cpuif.resp_buffer_size)-1}}:0]].rdata <= cpuif_rd_data;
+
+            end else if(cpuif_wr_ack) begin
+                axil_resp_buffer[axil_resp_wptr[{{clog2(cpuif.resp_buffer_size)-1}}:0]].is_wr <= '1;
+                axil_resp_buffer[axil_resp_wptr[{{clog2(cpuif.resp_buffer_size)-1}}:0]].err <= cpuif_wr_err;
+            end
+            {%- if is_pow2(cpuif.resp_buffer_size) %}
+            axil_resp_wptr <= axil_resp_wptr + 1'b1;
+            {%- else %}
+            if(axil_resp_wptr[{{clog2(cpuif.resp_buffer_size)-1}}:0] == {{cpuif.resp_buffer_size-1}}) begin
+                axil_resp_wptr[{{clog2(cpuif.resp_buffer_size)-1}}:0] <= '0;
+                axil_resp_wptr[{{clog2(cpuif.resp_buffer_size)}}] <= ~axil_resp_wptr[{{clog2(cpuif.resp_buffer_size)}}];
+            end else begin
+                axil_resp_wptr[{{clog2(cpuif.resp_buffer_size)-1}}:0] <= axil_resp_wptr[{{clog2(cpuif.resp_buffer_size)-1}}:0] + 1'b1;
+            end
+            {%- endif %}
+        end
+
+        // Advance read pointer when acknowledged
+        if(axil_resp_acked) begin
+            {%- if is_pow2(cpuif.resp_buffer_size) %}
+            axil_resp_rptr <= axil_resp_rptr + 1'b1;
+            {%- else %}
+            if(axil_resp_rptr[{{clog2(cpuif.resp_buffer_size)-1}}:0] == {{cpuif.resp_buffer_size-1}}) begin
+                axil_resp_rptr[{{clog2(cpuif.resp_buffer_size)-1}}:0] <= '0;
+                axil_resp_rptr[{{clog2(cpuif.resp_buffer_size)}}] <= ~axil_resp_rptr[{{clog2(cpuif.resp_buffer_size)}}];
+            end else begin
+                axil_resp_rptr[{{clog2(cpuif.resp_buffer_size)-1}}:0] <= axil_resp_rptr[{{clog2(cpuif.resp_buffer_size)-1}}:0] + 1'b1;
+            end
+            {%- endif %}
+        end
+    end
+end
+
+always_comb begin
+    axil_resp_acked = '0;
+    {{cpuif.signal("bvalid")}} = '0;
+    {{cpuif.signal("rvalid")}} = '0;
+    if(axil_resp_rptr != axil_resp_wptr) begin
+        if(axil_resp_buffer[axil_resp_rptr[{{clog2(cpuif.resp_buffer_size)-1}}:0]].is_wr) begin
+            {{cpuif.signal("bvalid")}} = '1;
+            if({{cpuif.signal("bready")}}) axil_resp_acked = '1;
+        end else begin
+            {{cpuif.signal("rvalid")}} = '1;
+            if({{cpuif.signal("rready")}}) axil_resp_acked = '1;
+        end
+    end
+
+    {{cpuif.signal("rdata")}} = axil_resp_buffer[axil_resp_rptr[{{clog2(cpuif.resp_buffer_size)-1}}:0]].rdata;
+    if(axil_resp_buffer[axil_resp_rptr[{{clog2(cpuif.resp_buffer_size)-1}}:0]].err) begin
+        {{cpuif.signal("bresp")}} = 2'b10;
+        {{cpuif.signal("rresp")}} = 2'b10;
+    end else begin
+        {{cpuif.signal("bresp")}} = 2'b00;
+        {{cpuif.signal("rresp")}} = 2'b00;
+    end
+end
+{%- endif %}

src/peakrdl_regblock/cpuif/base.py

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+from typing import TYPE_CHECKING, Optional
+import inspect
+import os
+
+import jinja2 as jj
+
+from ..utils import get_always_ff_event, clog2, is_pow2, roundup_pow2
+
+if TYPE_CHECKING:
+    from ..exporter import RegblockExporter
+    from systemrdl import SignalNode
+
+class CpuifBase:
+
+    # Path is relative to the location of the class that assigns this variable
+    template_path = ""
+
+    def __init__(self, exp:'RegblockExporter', cpuif_reset:Optional['SignalNode'], data_width:int=32, addr_width:int=32):
+        self.exp = exp
+        self.reset = cpuif_reset
+        self.data_width = data_width
+        self.addr_width = addr_width
+
+    @property
+    def port_declaration(self) -> str:
+        raise NotImplementedError()
+
+
+    def _get_template_path_class_dir(self) -> str:
+        """
+        Traverse up the MRO and find the first class that explicitly assigns
+        template_path. Returns the directory that contains the class definition.
+        """
+        for cls in inspect.getmro(self.__class__):
+            if "template_path" in cls.__dict__:
+                class_dir = os.path.dirname(inspect.getfile(cls))
+                return class_dir
+        raise RuntimeError
+
+
+    def get_implementation(self) -> str:
+        class_dir = self._get_template_path_class_dir()
+        loader = jj.FileSystemLoader(class_dir)
+        jj_env = jj.Environment(
+            loader=loader,
+            undefined=jj.StrictUndefined,
+        )
+
+        context = {
+            "cpuif": self,
+            "get_always_ff_event": lambda resetsignal : get_always_ff_event(self.exp.dereferencer, resetsignal),
+            "get_resetsignal": self.exp.dereferencer.get_resetsignal,
+            "clog2": clog2,
+            "is_pow2": is_pow2,
+            "roundup_pow2": roundup_pow2,
+        }
+
+        template = jj_env.get_template(self.template_path)
+        return template.render(context)

src/peakrdl_regblock/cpuif/passthrough/__init__.py

@@ -0,0 +1,21 @@
+from ..base import CpuifBase
+
+class PassthroughCpuif(CpuifBase):
+    template_path = "passthrough_tmpl.sv"
+
+    @property
+    def port_declaration(self) -> str:
+        lines = [
+            "input wire s_cpuif_req",
+            "input wire s_cpuif_req_is_wr",
+            f"input wire [{self.addr_width-1}:0] s_cpuif_addr",
+            f"input wire [{self.data_width-1}:0] s_cpuif_wr_data",
+            "output wire s_cpuif_req_stall_wr",
+            "output wire s_cpuif_req_stall_rd",
+            "output wire s_cpuif_rd_ack",
+            "output wire s_cpuif_rd_err",
+            f"output wire [{self.data_width-1}:0] s_cpuif_rd_data",
+            "output wire s_cpuif_wr_ack",
+            "output wire s_cpuif_wr_err",
+        ]
+        return ",\n".join(lines)

src/peakrdl_regblock/cpuif/passthrough/passthrough_tmpl.sv

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+assign cpuif_req = s_cpuif_req;
+assign cpuif_req_is_wr = s_cpuif_req_is_wr;
+assign cpuif_addr = s_cpuif_addr;
+assign cpuif_wr_data = s_cpuif_wr_data;
+assign s_cpuif_req_stall_wr = cpuif_req_stall_wr;
+assign s_cpuif_req_stall_rd = cpuif_req_stall_rd;
+assign s_cpuif_rd_ack = cpuif_rd_ack;
+assign s_cpuif_rd_err = cpuif_rd_err;
+assign s_cpuif_rd_data = cpuif_rd_data;
+assign s_cpuif_wr_ack = cpuif_wr_ack;
+assign s_cpuif_wr_err = cpuif_wr_err;