Switch to use regular non-namespaced package
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Alex Mykyta
216
src/peakrdl_regblock/dereferencer.py
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216
src/peakrdl_regblock/dereferencer.py
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from typing import TYPE_CHECKING, Union, Optional
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from systemrdl.node import AddrmapNode, FieldNode, SignalNode, RegNode
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from systemrdl.rdltypes import PropertyReference
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if TYPE_CHECKING:
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from .exporter import RegblockExporter
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from .hwif import Hwif
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from .field_logic import FieldLogic
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from .addr_decode import AddressDecode
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class Dereferencer:
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"""
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This class provides an interface to convert conceptual SystemRDL references
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into Verilog identifiers
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"""
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def __init__(self, exp:'RegblockExporter'):
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self.exp = exp
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@property
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def hwif(self) -> 'Hwif':
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return self.exp.hwif
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@property
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def address_decode(self) -> 'AddressDecode':
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return self.exp.address_decode
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@property
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def field_logic(self) -> 'FieldLogic':
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return self.exp.field_logic
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@property
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def top_node(self) -> AddrmapNode:
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return self.exp.top_node
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def get_value(self, obj: Union[int, FieldNode, SignalNode, PropertyReference]) -> str:
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"""
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Returns the Verilog string that represents the readable value associated
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with the object.
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If given a simple scalar value, then the corresponding Verilog literal is returned.
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If obj references a structural systemrdl object, then the corresponding Verilog
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expression is returned that represents its value.
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"""
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if isinstance(obj, int):
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# Is a simple scalar value
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return f"'h{obj:x}"
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if isinstance(obj, FieldNode):
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if obj.implements_storage:
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return self.field_logic.get_storage_identifier(obj)
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if self.hwif.has_value_input(obj):
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return self.hwif.get_input_identifier(obj)
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# Field does not have a storage element, nor does it have a HW input
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# must be a constant value as defined by its reset value
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reset_value = obj.get_property('reset')
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if reset_value is not None:
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return self.get_value(reset_value)
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else:
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# No reset value defined!
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obj.env.msg.warning(
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f"Field '{obj.inst_name}' is a constant but does not have a known value (missing reset). Assigning it a value of X.",
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obj.inst.inst_src_ref
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)
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return "'X"
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if isinstance(obj, SignalNode):
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# Signals are always inputs from the hwif
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return self.hwif.get_input_identifier(obj)
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if isinstance(obj, PropertyReference):
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if isinstance(obj.node, FieldNode):
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return self.get_field_propref_value(obj.node, obj.name)
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elif isinstance(obj.node, RegNode):
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return self.get_reg_propref_value(obj.node, obj.name)
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else:
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raise RuntimeError
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raise RuntimeError(f"Unhandled reference to: {obj}")
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def get_field_propref_value(self, field: FieldNode, prop_name: str) -> str:
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# Value reduction properties.
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# Wrap with the appropriate Verilog reduction operator
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if prop_name == "anded":
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val = self.get_value(field)
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return f"&({val})"
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elif prop_name == "ored":
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val = self.get_value(field)
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return f"|({val})"
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elif prop_name == "xored":
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val = self.get_value(field)
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return f"^({val})"
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# references that directly access a property value
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if prop_name in {
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'decrvalue',
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'enable',
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'haltenable',
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'haltmask',
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'hwenable',
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'hwmask',
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'incrvalue',
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'mask',
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'reset',
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'resetsignal',
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}:
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return self.get_value(field.get_property(prop_name))
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# Field Next
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if prop_name == "next":
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prop_value = field.get_property(prop_name)
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if prop_value is None:
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# unset by the user, points to the implied internal signal
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return self.field_logic.get_field_combo_identifier(field, "next")
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else:
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return self.get_value(prop_value)
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# References to another component value, or an implied input
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if prop_name in {'hwclr', 'hwset'}:
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prop_value = field.get_property(prop_name)
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if prop_value is True:
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# Points to inferred hwif input
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return self.hwif.get_implied_prop_input_identifier(field, prop_name)
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elif prop_value is False:
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# This should never happen, as this is checked by the compiler's validator
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raise RuntimeError
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else:
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return self.get_value(prop_value)
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# References to another component value, or an implied input
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# May have a complementary partner property
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complementary_pairs = {
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"we": "wel",
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"wel": "we",
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"swwe": "swwel",
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"swwel": "swwe",
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}
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if prop_name in complementary_pairs:
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prop_value = field.get_property(prop_name)
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if prop_value is True:
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# Points to inferred hwif input
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return self.hwif.get_implied_prop_input_identifier(field, prop_name)
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elif prop_value is False:
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# Try complementary property
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prop_value = field.get_property(complementary_pairs[prop_name])
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if prop_value is True:
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# Points to inferred hwif input
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return f"!({self.hwif.get_implied_prop_input_identifier(field, complementary_pairs[prop_name])})"
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elif prop_value is False:
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# This should never happen, as this is checked by the compiler's validator
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raise RuntimeError
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else:
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return f"!({self.get_value(prop_value)})"
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else:
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return self.get_value(prop_value)
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if prop_name == "swacc":
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return self.field_logic.get_swacc_identifier(field)
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if prop_name == "swmod":
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return self.field_logic.get_swmod_identifier(field)
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# translate aliases
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aliases = {
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"saturate": "incrsaturate",
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"threshold": "incrthreshold",
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}
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prop_name = aliases.get(prop_name, prop_name)
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# Counter properties
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if prop_name == 'incr':
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return self.field_logic.get_counter_incr_strobe(field)
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if prop_name == 'decr':
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return self.field_logic.get_counter_decr_strobe(field)
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if prop_name in {
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'decrsaturate',
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'decrthreshold',
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'incrsaturate',
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'incrthreshold',
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'overflow',
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'underflow',
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}:
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return self.field_logic.get_field_combo_identifier(field, prop_name)
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raise RuntimeError(f"Unhandled reference to: {field}->{prop_name}")
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def get_reg_propref_value(self, reg: RegNode, prop_name: str) -> str:
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if prop_name in {'halt', 'intr'}:
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return self.hwif.get_implied_prop_output_identifier(reg, prop_name)
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raise NotImplementedError
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def get_access_strobe(self, obj: Union[RegNode, FieldNode]) -> str:
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"""
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Returns the Verilog string that represents the register's access strobe
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"""
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return self.address_decode.get_access_strobe(obj)
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def get_resetsignal(self, obj: Optional[SignalNode]) -> str:
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"""
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Returns a normalized active-high reset signal
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"""
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if isinstance(obj, SignalNode):
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s = self.get_value(obj)
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if obj.get_property('activehigh'):
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return s
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else:
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return f"~{s}"
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# default reset signal
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return "rst"
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