Switch to use regular non-namespaced package

.github/workflows/build.yml

@@ -65,7 +65,7 @@ jobs:
 
       - name: Run Lint
         run: |
-          pylint --rcfile tests/pylint.rc peakrdl
+          pylint --rcfile tests/pylint.rc peakrdl_regblock
 
 #-------------------------------------------------------------------------------
   mypy:
@@ -83,7 +83,7 @@ jobs:
 
       - name: Type Check
         run: |
-          mypy --config-file tests/mypy.ini src/peakrdl
+          mypy --config-file tests/mypy.ini src/peakrdl_regblock
 
 #-------------------------------------------------------------------------------
   build_sdist:

MANIFEST.in

@@ -1,2 +1,2 @@
-recursive-include src/peakrdl/regblock *.sv
+recursive-include src/peakrdl_regblock *.sv
 prune tests

docs/api.rst

@@ -1,5 +1,5 @@
 Exporter API
 ============
 
-.. autoclass:: peakrdl.regblock.RegblockExporter
+.. autoclass:: peakrdl_regblock.RegblockExporter
     :members:

docs/cpuif/apb3.rst

@@ -8,14 +8,14 @@ CPU interface.
 The APB3 CPU interface comes in two i/o port flavors:
 
 SystemVerilog Interface
-    Class: :class:`peakrdl.regblock.cpuif.apb3.APB3_Cpuif`
+    Class: :class:`peakrdl_regblock.cpuif.apb3.APB3_Cpuif`
 
     Interface Definition: :download:`apb3_intf.sv <../../tests/lib/cpuifs/apb3/apb3_intf.sv>`
 
 Flattened inputs/outputs
     Flattens the interface into discrete input and output ports.
 
-    Class: :class:`peakrdl.regblock.cpuif.apb3.APB3_Cpuif_flattened`
+    Class: :class:`peakrdl_regblock.cpuif.apb3.APB3_Cpuif_flattened`
 
 
 .. warning::

docs/cpuif/axi4lite.rst

@@ -10,14 +10,14 @@ CPU interface.
 The AXI4-Lite CPU interface comes in two i/o port flavors:
 
 SystemVerilog Interface
-    Class: :class:`peakrdl.regblock.cpuif.axi4lite.AXI4Lite_Cpuif`
+    Class: :class:`peakrdl_regblock.cpuif.axi4lite.AXI4Lite_Cpuif`
 
     Interface Definition: :download:`axi4lite_intf.sv <../../tests/lib/cpuifs/axi4lite/axi4lite_intf.sv>`
 
 Flattened inputs/outputs
     Flattens the interface into discrete input and output ports.
 
-    Class: :class:`peakrdl.regblock.cpuif.axi4lite.AXI4Lite_Cpuif_flattened`
+    Class: :class:`peakrdl_regblock.cpuif.axi4lite.AXI4Lite_Cpuif_flattened`
 
 
 Pipelined Performance

docs/cpuif/customizing.rst

@@ -28,7 +28,7 @@ Rather than rewriting a new CPU interface definition, you can extend and adjust
 
 .. code-block:: python
 
-    from peakrdl.regblock.cpuif.axi4lite import AXI4Lite_Cpuif
+    from peakrdl_regblock.cpuif.axi4lite import AXI4Lite_Cpuif
 
     class My_AXI4Lite(AXI4Lite_Cpuif):
         @property
@@ -70,7 +70,7 @@ you can define your own.
 
 2. Create a Python class that defines your CPUIF
 
-    Extend your class from :class:`peakrdl.regblock.cpuif.CpuifBase`.
+    Extend your class from :class:`peakrdl_regblock.cpuif.CpuifBase`.
     Define the port declaration string, and provide a reference to your template file.
 
 3. Use your new CPUIF definition when exporting!

docs/cpuif/passthrough.rst

@@ -4,6 +4,6 @@ CPUIF Passthrough
 This CPUIF mode bypasses the protocol converter stage and directly exposes the
 internal CPUIF handshake signals to the user.
 
-Class: :class:`peakrdl.regblock.cpuif.passthrough.PassthroughCpuif`
+Class: :class:`peakrdl_regblock.cpuif.passthrough.PassthroughCpuif`
 
 For more details on the protocol itself, see: :ref:`cpuif_protocol`.

docs/index.rst

@@ -37,8 +37,8 @@ implementation from SystemRDL source.
     :emphasize-lines: 2-3, 23-27
 
     from systemrdl import RDLCompiler, RDLCompileError
-    from peakrdl.regblock import RegblockExporter
+    from peakrdl_regblock import RegblockExporter
-    from peakrdl.regblock.cpuif.apb3 import APB3_Cpuif
+    from peakrdl_regblock.cpuif.apb3 import APB3_Cpuif
 
     input_files = [
         "PATH/TO/my_register_block.rdl"

setup.py

@@ -5,7 +5,7 @@ with open("README.md", "r", encoding='utf-8') as fh:
     long_description = fh.read()
 
 
-with open(os.path.join("src/peakrdl/regblock", "__about__.py"), encoding='utf-8') as f:
+with open(os.path.join("src/peakrdl_regblock", "__about__.py"), encoding='utf-8') as f:
     v_dict = {}
     exec(f.read(), v_dict)
     version = v_dict['__version__']
@@ -20,7 +20,7 @@ setuptools.setup(
     long_description_content_type="text/markdown",
     url="https://github.com/SystemRDL/PeakRDL-regblock",
     package_dir={'': 'src'},
-    packages=setuptools.find_namespace_packages("src", include=['peakrdl.*']),
+    packages=setuptools.find_packages("src"),
     include_package_data=True,
     python_requires='>=3.6',
     install_requires=[

src/peakrdl_regblock/exporter.py

@@ -54,7 +54,7 @@ class RegblockExporter:
         output_dir: str
             Path to the output directory where generated SystemVerilog will be written.
             Output includes two files: a module definition and package definition.
-        cpuif_cls: :class:`peakrdl.regblock.cpuif.CpuifBase`
+        cpuif_cls: :class:`peakrdl_regblock.cpuif.CpuifBase`
             Specify the class type that implements the CPU interface of your choice.
             Defaults to AMBA APB3.
         module_name: str

tests/lib/base_testcase.py

@@ -9,7 +9,7 @@ import pathlib
 import pytest
 from systemrdl import RDLCompiler
 
-from peakrdl.regblock import RegblockExporter
+from peakrdl_regblock import RegblockExporter
 from .cpuifs.base import CpuifTestMode
 from .cpuifs.apb3 import APB3
 
@@ -72,7 +72,7 @@ class BaseTestCase(unittest.TestCase):
     @classmethod
     def _export_regblock(cls):
         """
-        Call the peakrdl.regblock exporter to generate the DUT
+        Call the peakrdl_regblock exporter to generate the DUT
         """
         this_dir = cls.get_testcase_dir()
 

tests/lib/cpuifs/apb3/__init__.py

@@ -1,6 +1,6 @@
 from ..base import CpuifTestMode
 
-from peakrdl.regblock.cpuif.apb3 import APB3_Cpuif, APB3_Cpuif_flattened
+from peakrdl_regblock.cpuif.apb3 import APB3_Cpuif, APB3_Cpuif_flattened
 
 class APB3(CpuifTestMode):
     cpuif_cls = APB3_Cpuif

tests/lib/cpuifs/axi4lite/__init__.py

@@ -1,6 +1,6 @@
 from ..base import CpuifTestMode
 
-from peakrdl.regblock.cpuif.axi4lite import AXI4Lite_Cpuif, AXI4Lite_Cpuif_flattened
+from peakrdl_regblock.cpuif.axi4lite import AXI4Lite_Cpuif, AXI4Lite_Cpuif_flattened
 
 class AXI4Lite(CpuifTestMode):
     cpuif_cls = AXI4Lite_Cpuif

tests/lib/cpuifs/base.py

@@ -4,12 +4,12 @@ import inspect
 
 import jinja2 as jj
 
-from peakrdl.regblock.cpuif.base import CpuifBase
+from peakrdl_regblock.cpuif.base import CpuifBase
 
 from ..sv_line_anchor import SVLineAnchor
 
 if TYPE_CHECKING:
-    from peakrdl.regblock import RegblockExporter
+    from peakrdl_regblock import RegblockExporter
     from ..sim_testcase import SimTestCase
 
 class CpuifTestMode:

tests/lib/cpuifs/passthrough/__init__.py

@@ -1,6 +1,6 @@
 from ..base import CpuifTestMode
 
-from peakrdl.regblock.cpuif.passthrough import PassthroughCpuif
+from peakrdl_regblock.cpuif.passthrough import PassthroughCpuif
 
 class Passthrough(CpuifTestMode):
     cpuif_cls = PassthroughCpuif

tests/pylint.rc

@@ -92,7 +92,6 @@ disable=
 
         # Noise / Don't care
         no-else-return,
-        no-self-use,
         unused-variable,
         invalid-name,
         missing-docstring,

tests/run.sh

@@ -23,7 +23,7 @@ export SKIP_SYNTH_TESTS=1
 pytest --workers auto
 
 # Run lint
-pylint --rcfile $this_dir/pylint.rc ../src/peakrdl
+pylint --rcfile $this_dir/pylint.rc ../src/peakrdl_regblock
 
 # Run static type checking
-mypy $this_dir/../src/peakrdl
+mypy $this_dir/../src/peakrdl_regblock

tests/test_user_cpuif/testcase.py

@@ -1,6 +1,6 @@
 import os
 
-from peakrdl.regblock.cpuif.apb3 import APB3_Cpuif
+from peakrdl_regblock.cpuif.apb3 import APB3_Cpuif
 from ..lib.cpuifs.apb3 import APB3
 from ..lib.base_testcase import BaseTestCase