bslathi19/PeakRDL-regblock
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Add width cast to address decode loop iterators. #92

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This commit is contained in:
Alex Mykyta
2024-12-19 21:49:23 -08:00
parent e788e7cafd
commit 8d82eb29d9
2 changed files with 4 additions and 3 deletions
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5
src/peakrdl_regblock/addr_decode.py
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@@ -159,12 +159,13 @@ class DecodeLogicGenerator(RDLForLoopGenerator):
def _get_address_str(self, node: 'AddressableNode', subword_offset: int=0) -> str:
expr_width = self.addr_decode.exp.ds.addr_width
a = str(SVInt(
node.raw_absolute_address - self.addr_decode.top_node.raw_absolute_address + subword_offset,
self.addr_decode.exp.ds.addr_width
expr_width
))
for i, stride in enumerate(self._array_stride_stack):
a += f" + i{i}*{SVInt(stride, self.addr_decode.exp.ds.addr_width)}"
a += f" + ({expr_width})'(i{i}) * {SVInt(stride, expr_width)}"
return a